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ics for communications digital answering machine with full duplex speakerphone sam ec psb 4860 version 2.1 data sheet 10.97 ds 1
edition 10.97 this edition was realized using the software system framemaker a . published by siemens ag, hl ts ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. psb 4860 revision history: current version: 10.97 previous version: preliminary data sheet 09.97 page (in previous version) page (in new version) subjects (major changes since last revision) index added
psb 4860 table of contents page semiconductor group 3 10.97 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.6.1 analog featurephone with digital answering machine . . . . . . . . . . . . . . .19 1.6.2 featurephone with digital answering machine for isdn terminal . . . . . .21 1.6.3 dect basestation with integrated digital answering machine . . . . . . . . .22 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.1.1 full duplex speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.1.2 echo cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.1.3 echo suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.1.4 line echo canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.1.5 dtmf detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.1.6 cng detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.1.7 alert tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 2.1.8 cpt detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.1.9 caller id decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.1.10 dtmf generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.1.11 speech coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.1.12 speech decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.1.13 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.1.14 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.1.15 universal attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.1.16 automatic gain control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.1.17 equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2 memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2.2.1 file definition and access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.2.2 user data word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2.2.3 high level memory management commands . . . . . . . . . . . . . . . . . . . . .67 2.2.4 low level memory management commands . . . . . . . . . . . . . . . . . . . . . .75 2.2.5 execution time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 2.2.6 special notes on file commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 2.3 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.3.1 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.3.2 sps control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.3.3 reset and power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.3.4 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 2.3.5 abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
psb 4860 table of contents page semiconductor group 4 10.97 2.3.6 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.3.7 hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.3.8 frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.3.9 clock tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 2.3.10 dependencies of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 2.4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.4.1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.4.2 ssdi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 2.4.3 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 2.4.4 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.4.5 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 2.4.6 auxiliary parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 3 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 3.1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 3.2 hardware configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 3.3 read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.3.1 register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.3.2 register naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 4.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 ) iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. digitape ? , musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? are trademarks of siemens ag.
psb 4860 list of figures page semiconductor group 5 10.97 general figure 1: pin configuration of psb 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2: logic symbol of psb 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3: block diagram of psb 4860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4: analog full duplex speakerphone with digital answering machine . . . . 20 figure 5: featurephone with answering machine for isdn terminal . . . . . . . . . . . 21 figure 6: dect basestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 functional units figure 7: functional units - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8: functional units - recording a phone conversation . . . . . . . . . . . . . . . . 25 figure 9: functional units - simultaneous internal and external call . . . . . . . . . . . 26 figure 10: speakerphone - signal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11: speakerphone - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12: echo cancellation unit - block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13: echo cancellation unit - typical room impulse response . . . . . . . . . . . 29 figure 14: echo suppression unit - states of operation. . . . . . . . . . . . . . . . . . . . . . 30 figure 15: echo suppression unit - signal flow graph . . . . . . . . . . . . . . . . . . . . . . 31 figure 16: speech detector - signal flow graph . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17: speech comparator - block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18: speech comparator - interdependence of parameters . . . . . . . . . . . . . . 36 figure 19: echo suppression unit - automatic gain control. . . . . . . . . . . . . . . . . . . 39 figure 20: line echo cancellation unit - block diagram. . . . . . . . . . . . . . . . . . . . . . 42 figure 21: dtmf detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22: cng detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23: alert tone detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 24: cpt detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25: cpt detector - cooked mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 26: caller id decoder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 27: dtmf generator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 28: speech coder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 29: speech decoder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 30: analog front end interface - block diagram . . . . . . . . . . . . . . . . . . . . . . 55 figure 31: digital interface - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 32: universal attenuator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 33: automatic gain control unit - block diagram . . . . . . . . . . . . . . . . . . . . . 59 figure 34: equalizer - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 memory management figure 35: memory management - data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 36: memory management - directory structure . . . . . . . . . . . . . . . . . . . . . . . 63 figure 37: audio file organization - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 38: binary file organization - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
psb 4860 list of figures page semiconductor group 6 10.97 figure 39: phrase file organization - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 miscellaneous figure 40: operation modes - state chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 interfaces figure 41: iom ? -2 interface - frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 42: iom ? -2 interface - frame start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 43: iom ? -2 interface - single clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 44: iom ? -2 interface - double clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 45: ssdi interface - transmitter timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 46: ssdi interface - active pulse selection . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 47: ssdi interface - receiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 48: analog front end interface - frame structure . . . . . . . . . . . . . . . . . . . . . 92 figure 49: analog front end interface - frame start . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 50: analog front end interface - data transfer . . . . . . . . . . . . . . . . . . . . . . . 93 figure 51: status register read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 52: data read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 53: register write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 54: configuration register read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 55: configuration register write access or register read command . . . . . 96 figure 56: aram/dram interface - connection diagram. . . . . . . . . . . . . . . . . . . . . 99 figure 57: aram/dram interface - read cycle timing . . . . . . . . . . . . . . . . . . . . . 100 figure 58: aram/dram interface - write cycle timing . . . . . . . . . . . . . . . . . . . . . 101 figure 59: aram/dram interface - refresh cycle timing . . . . . . . . . . . . . . . . . . . 101 figure 60: eprom interface - connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 61: eprom interface - read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 62: flash memory interface - connection diagram . . . . . . . . . . . . . . . . . . . 103 figure 63: flash memory interface - multiple devices . . . . . . . . . . . . . . . . . . . . . . 104 figure 64: flash memory interface - command write. . . . . . . . . . . . . . . . . . . . . . . 105 figure 65: flash memory interface - address write . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 66: flash memory interface - data write . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 67: flash memory interface - data read . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 68: auxiliary parallel port - multiplex mode . . . . . . . . . . . . . . . . . . . . . . . . . 108 electrical characteristics figure 69: input/output waveforms for ac-tests . . . . . . . . . . . . . . . . . . . . . . . . . . 227 timing diagrams figure 70: oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 71: ssdi/iom ? -2 interface - bit synchronization timing . . . . . . . . . . . . . . . 232 figure 72: ssdi/iom ? -2 interface - frame synchronization timing . . . . . . . . . . . . 232 figure 73: ssdi interface - strobe timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
psb 4860 list of figures page semiconductor group 7 10.97 figure 74: serial control interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 75: analog front end interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 figure 76: memory interface - dram read access . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 77: memory interface - dram write access . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 78: memory interface - dram refresh cycle . . . . . . . . . . . . . . . . . . . . . . . 239 figure 79: memory interface - eprom read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 figure 80: memory interface - samsung command write . . . . . . . . . . . . . . . . . . . 241 figure 81: memory interface - samsung address write . . . . . . . . . . . . . . . . . . . . . 242 figure 82: memory interface - samsung data write . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 83: memory interface - samsung data read . . . . . . . . . . . . . . . . . . . . . . . . 244 figure 84: auxiliary parallel port - multiplex mode . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 85: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
psb 4860 list of tables page semiconductor group 8 10.97 general table 1: pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 functional units table 2: signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 3: echo cancellation unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 4: speech detector parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 5: speech comparator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 6: attenuation control unit parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 7: sps output encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 8: automatic gain control parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 9: fixed gain parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 10: speakerphone control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 11: line echo cancellation unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 12: dtmf detector control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 13: dtmf detector results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 14: dtmf detector parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 15: cng detector registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 16: cng detector result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 17: alert tone detector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 18: alert tone detector results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 19: cpt detector result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 20: cpt detector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 21: caller id decoder modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 22: caller id decoder status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 23: caller id decoder registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 24: dtmf generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 25: speech coder status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 26: speech coder registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 27: speech decoder registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 28: analog front end interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 29: digital interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 30: universal attenuator registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 31: automatic gain control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 32: equalizer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 memory management - general table 33: memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 34: memory management status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 35: memory management parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 memory management - commands table 36: initialize memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
psb 4860 semiconductor group 9 10.97 table 37: initialize memory results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 38: activate memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 39: activate memory results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 40: activate memory result interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 41: open file parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 42: open next free file parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 43: open next free file results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 44: seek parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 45: cut file parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 46: compress file parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 47: memory status parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 48: memory status results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 49: garbage collection parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 50: access file descriptor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 51: access file descriptor results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 52: read data parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 53: read data results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 54: write data parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 55: set address parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 56: dma read parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 57: dma read results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 58: dma write parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 59: block erase parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 60: execution times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 miscellaneous table 61: real time clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 table 62: sps registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 table 63: power down bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 table 64: interrupt source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 65: hardware configuration checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 66: frame synchronization selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 67: dependencies of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 68: file command classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 69: module weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 interfaces table 70: ssdi vs. iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table 71: iom ? -2 interface registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 72: ssdi interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 73: control of als amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 74: analog front end interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 75: analog front end interface clock cycles. . . . . . . . . . . . . . . . . . . . . . . . . .93
psb 4860 semiconductor group 10 10.97 table 76: command words for register access . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 77: address field w for configuration register write . . . . . . . . . . . . . . . . . . .97 table 78: address field r for configuration register read . . . . . . . . . . . . . . . . . . .97 table 79: supported memory configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 80: address line usage (aram/dram mode) . . . . . . . . . . . . . . . . . . . . . . .100 table 81: refresh frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 table 82: address line usage (samsung mode). . . . . . . . . . . . . . . . . . . . . . . . . . .103 table 83: flash memory command summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 table 84: static mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 table 85: multiplex mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 table 86: signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 electrical characteristics table 87: status register update timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
semiconductor group 11 10.97 psb 4860 overview 1overview general general combined with an analog front end the psb 4860 provides a solution for embedded or stand alone answering machine applications. together with a standard microcontroller for analog telephones these two chips form the core of a featurephone with full duplex speakerphone and answering machine capabilities. the chip features recording by digitape ? , a family of high performance algorithms. messages recorded with digitape ? can be played back with variable speed without pitch alteration. messages recorded with a higher bitrate can be converted into messages with a lower bitrate arbitrarily. current members of digitape (tm) span the range from 3.3 kbit/s to 10.3 kbit/s. furthermore the psb 4860, v2.1 has a full duplex speakerphone, a caller id decoder, dtmf recognition and generation and call progress tone detection. the frequency response of cheap microphones or loudspeakers can be corrected by a programmable equalizer. messages and user data can be stored in aram/dram or flash memory which can be directly connected to the psb 4860. the psb 4860 also supports a voice prompt eprom for fixed announcements. the psb 4860 provides an iom ? -2 compatible interface with two channels for speech data. alternatively to the iom ? -2 compatible interface the psb 4860 supports a simple serial data interface (ssdi) with separate strobe signals for each direction (linear pcm data, one channel). a separate interface is used for a glueless connection to the psb 4851. the chip is programmed by a simple four wire serial control interface and can inform the microcontroller of new events by an interrupt signal. for data retention the psb 4860 supports a power down mode where only the real time clock and the memory refresh (in case of aram/dram) are operational. the psb 4860 supports interface pins to +5 v levels.
p-mqfp-80 semiconductor group 12 10.97 digital answering machine with full duplex speakerphone sam ec psb 4860 version 2.1 cmos type package psb 4860 p-mqfp-80 1.1 features digital functions ? high performance recording by digitape ? ? selectable compression rate (3.3 kbit/s, 10.3 kbit/s) ? variable playback speed ? support for aram or flash memory ? optional voice prompt eprom ? full duplex speakerphone ? dtmf generation and detection ? call progress tone detection ? caller id recognition ? direct memory access ? real time clock ? equalizer ? automatic gain control ? automatic timestamp ? auxiliary parallel port ? ultra low power refresh mode general features ? ssdi/iom ? -2 compatible interface ? serial control interface for programming
psb 4860 overview semiconductor group 13 10.97 1.2 pin configuration (top view) figure 1 pin configuration of psb 4860 110 20 21 30 40 41 60 50 61 70 80 v dda xtal 1 xtal 2 osc 1 osc 2 v ssa sclk sdr v dd afedd afedu v dd v ss v dd v ss afefs afeclk fsc du/dx dd/dr dxst drst v dd v ss dcl w /fwe frdy vprd /fcle ras /foe cas 1 /fcs sps 0 sps 1 v dd v ss md 1 md 2 ma 3 ma 2 ma 1 ma 0 md 7 md 6 md 5 md 4 md 3 v dd v ss v dd v ss v ss v ss ro v dd ma 4 ma 5 ma 6 v dd ma 8 v ss ma 15 v ss ma 7 ma 9 ma 10 v dd ma 12 ma 13 ma 14 v ss ma 11 v ddp rst clk v ss md 0 v ddp int sdx cs cas 0 /ale sam ec psb 4860
psb 4860 overview semiconductor group 14 10.97 1.3 pin definitions and functions table 1 pin definitions and functions pin no. p-mqfp-80 symbol dir. reset function 41, 80 v ddp -- power supply (5v %) power supply for the interface. 7, 15, 21, 29, 39, 49, 58, 61, 67, 73 v dd -- power supply (3.0 v - 3.6 v ) power supply for logic. 1 v dda -- power supply (3.0 v - 3.6 v) power supply for clock generator. 4 v ssa -- power supply (0 v) ground for clock generator. 9, 16, 22, 30, 40, 48, 57, 59, 60, 78, 66, 72 v ss -- power supply (0 v) ground for logic and interface. 17 afefs o l analog frontend frame sync: 8 khz frame synchronization signal for the analog front end. 18 afeclk o l analog frontend clock: clock signal for the analog front end. 19 afedd o l analog frontend data downstream: data output to the analog frontend. 20 afedu i - analog frontend data upstream: data input from the analog frontend. 79 rst i - reset: active high reset signal. 23 fsc i - data frame synchronization: 8 khz frame synchronization signal (iom ? -2 and ssdi mode). 24 dcl i - data clock: data clock of the serial data interface. 10
psb 4860 overview semiconductor group 15 10.97 26 dd/dr i /od i - iom ? -2 compatible mode: receive data from iom ? -2 controlling device. ssdi mode: receive data of the strobed serial data interface. 25 du/dx i /od o/ od - iom ? -2 compatible mode: transmit data to iom ? -2 controlling device. ssdi mode: transmit data of the strobed serial data interface. 27 dxst o l dx strobe: strobe for dx in ssdi interface mode. 28 drst i - dr strobe: strobe for dr in ssdi interface mode. 14 cs i- chip select: select signal of the serial control interface (sci). 11 sclk i - serial clock: clock signal of the serial control interface (sci). 13 sdr i - serial data receive: data input of the serial control interface (sci). 12 sdx o/ od h serial data transmit: data output of the serial control interface (sci). 10 int o/ od h interrupt new status available. table 1 pin definitions and functions
psb 4860 overview semiconductor group 16 10.97 52 53 54 55 62 63 64 65 68 69 70 71 74 75 76 77 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ma 10 ma 11 ma 12 ma 13 ma 14 ma 15 i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o l 1) l l l l l l l l l l l l l l l memory address 0-15: multiplexed address outputs for aram, dram access. non-multiplexed address outputs for voice prompt eprom. auxiliary parallel port: general purpose i/o. 42 43 44 45 46 47 50 51 md 0 md 1 md 2 md 3 md 4 md 5 md 6 md 7 i /o i /o i /o i /o i /o i /o i /o i /o - - - - - - - - memory data 0-7: memory (aram, dram, flash memory, eprom) data bus. 35 36 cas 0 / ale cas 1 / fcs o o h 2) aram, dram: column address strobe for memory bank 0 or 1. flash memory: address latch enable for address lines a 16 -a 23 . chip select signal for flash memory 34 ras / foe oh 2 ) aram, dram: row address strobe for both memory banks. flash memory: output enable signal for flash memory. 33 vprd / fcle oh 2 ) aram, dram: read signal for voice prompt eprom. flash memory: command latch enable for flash memory. table 1 pin definitions and functions
psb 4860 overview semiconductor group 17 10.97 1) these lines are driven low with 125 m a until the mode (address lines or auxiliary port) is defined. 2) these lines are driven high with 70 m a during reset. 32 w /fwe oh 2 ) aram, dram: write signal for all memory banks. flash memory: write signal for flash memory. 31 frdy i - flash memory ready input for ready/busy signal of flash memory 5 6 osc 1 osc 2 i o - z auxiliary oscillator: oscillator loop for 32.768 khz crystal. 8clki- alternative afeclk source 13,824 mhz 2 3 xtal 1 xtal 2 i o - z oscillator: xtal 1 : external clock or input of oscillator loop. xtal 2 : output of oscillator loop for crystal. 37 38 sps 0 sps 1 o o l l multipurpose outputs: general purpose, speakerphone, address lines or status 56 ro o - reserved output must be left open. table 1 pin definitions and functions
psb 4860 overview semiconductor group 18 10.97 1.4 logic symbol 1 figure 2 logic symbol of psb 4860 du/dx dd/dr dcl fsc sdx sdr sclk cs iom ? -2 sci afeclk afefs afedu afedd psb ma 0 -ma 15 md 0 -md 7 cas 0 / ale cas 1 / fcs foe ras / vprd/ fcle w / fwe memory v dda v dd v ss osc 2 osc 1 xtal 1 xtal 2 rst ssdi 4851 int frdy dxst drst clk psb 4860
psb 4860 overview semiconductor group 19 10.97 1.5 functional block diagram figure 3 block diagram of psb 4860 1.6 system integration the psb 4860 combined with an analog front end (psb 4851) can be used in a variety of applications. this combination offers outstanding features like full duplex speakerphone and emergency operation. some applications are given in the following sections. 1.6.1 analog featurephone with digital answering machine figure 4 shows an example of an analog telephone system. the telephone can operate during power failure by line powering. in this case only the handset and ringer circuit are active. all other parts of the chipset are shut down leaving enough power for the external microcontroller to perform basic tasks like keyboard monitoring. du/dx dd/dr dcl fsc sdx sdr sclk cs afeclk afefs afedu afedd ma 0 -ma 15 md 0 -md 7 cas 0 / ale cas 1 / fcs foe ras /vprd / fcle w / fwe osc 2 osc 1 xtal 1 xtal 2 rst dsp memory interface reset and timing unit data interface control interface analog front end interface int frdy dxst drst
psb 4860 overview semiconductor group 20 10.97 for answering machine operation the voice data is stored in aram or flash memory devices. in addition, voice prompts can be played back from an optional voice prompt eprom. if flash memory is used the functionality of the voice prompt eprom can be realized by the flash memory devices. the microcontroller can use the memory attached to the psb 4860/psb 4851 to store and retrieve binary data. figure 4 analog full duplex speakerphone with digital answering machine voice prompt aram flash memory eprom microcontroller 077-3445 line tip/ ring psb 4860 psb 4851
psb 4860 overview semiconductor group 21 10.97 1.6.2 featurephone with digital answering machine for isdn terminal figure 5 shows an isdn featurephone that takes full advantage of two simultaneous connections. in this application one channel of the psb 4851 interfaces to the handset and speakerphone while the other provides an interface for an external analog device (e.g. fax machine). figure 5 featurephone with answering machine for isdn terminal in addition, the two channels of the psb 4851 can be used for holding two connections simultaneously. one connection can be switched to the handset and the other to the speakerphone box. local three party conferences are also possible. flash memory psb 4860 psb 4851 microcontroller 077-3445 iom ? -2 sci psb 2186 isac ? -s te s 0 -bus power controller psb 2120/1 slic pots
psb 4860 overview semiconductor group 22 10.97 1.6.3 dect basestation with integrated digital answering machine figure 6 shows a dect basestation based on the psb 4860/psb 4851 chipset. in this application it is possible to service both an external call and an internal call at the same time. for programming the serial control interface (sci) is used while voice data is transferred via the strobed serial data interface (ssdi/iom ? -2). figure 6 dect basestation flash memory microcontroller 077-3445 antenna ssdi/iom ? -2 sci burstmode controller dect hf line tip/ ring psb 4860 psb 4851
psb 4860 functional description semiconductor group 23 10.97 2 functional description functional units functional units the psb 4860 contains several functional units that can be combined with almost no restrictions to perform a given task. figure 7 gives an overview of the important functional units. figure 7 functional units - overview dtmf generator dtmf detector speech coder speaker- phone cid decoder speech decoder cpt detector line line micro- loud- ssdi/iom ? -2 iom ? -2 s 1 s 3 s 5 s 7 s 11 s 12 s 10 s 9 s 13 s 4 s 2 s 8 s 6 signal summation: signal sources: s 1 ,...,s 18 in out speaker phone i 1 i 2 i 3 line side acoustic side memory sci i 1 i 1 i 1 i 2 i 3 i 1 i 2 i 3 channel 2 channel 1 i 3 i 4 i 1 i 2 i 1 i 2 i 3 i 1 i 2 i 3 i 1 i 2 i 1 alert tone detector cng detector i 1 i 1 universal attenuator i 1 s 14 line echo canceller i 1 i 2 s 15 agc i 1 i 2 s 17 equalizer i 1 s 18 s 16
psb 4860 functional description semiconductor group 24 10.97 each unit has one or more signal inputs (denoted by i). most units have at least one signal output (denoted by s). any input i can be connected to any signal output s. in addition to the signals shown in figure 7 there is also the signal s 0 (silence), which is useful at signal summation points. table 2 lists the available signals within the psb 4860 according to their reference points. table 2 signal summary signal description s 0 silence s 1 analog line input (channel 1 of psb 4851 interface) s 2 analog line output (channel 1 of psb 4851 interface) s 3 microphone input (channel 2 of psb 4851 interface) s 4 loudspeaker/handset output (channel 2 of psb 4851 interface) s 5 serial interface input, channel 1 s 6 serial interface output, channel 1 s 7 serial interface input, channel 2 s 8 serial interface output, channel 2 s 9 dtmf generator output s 10 dtmf generator auxiliary output s 11 speakerphone output (acoustic side) s 12 speakerphone output (line side) s 13 speech decoder output s 14 universal attenuator output s 15 line echo canceller output s 16 automatic gain control output (after gain stage) s 17 automatic gain control output (before gain stage) s 18 equalizer output
psb 4860 functional description semiconductor group 25 10.97 the following figures show the connections for two typical states during operation. units that are not needed are not shown. inputs that are not needed are connected to s 0 which provides silence (denoted by 0). in figure 8 a hands-free phone conversation is currently in progress. the speech coder is used to record the signals of both parties. the alert tone detector is used to detect an alerting tone of an off-hook caller id request while the cid decoder decodes the actual data transmitted in this case. figure 8 functional units - recording a phone conversation alert tone detector speech coder speaker- phone cid decoder line echo canceller line line micro- loud- in out speaker phone line side acoustic side memory sci 0 0 0 0 0 0 agc
psb 4860 functional description semiconductor group 26 10.97 in figure 9 a phone conversation using the speakerphone is in progress. one party is using the base station of a dect system while the other party is using a mobile handset. at the same time an external call is serviced by the answering machine. in the current state a message (recorded or outgoing) is being played back. in this case the dtmf detector is used to detect signals for remote access while the cpt detector is used to determine the end of the external call. figure 9 functional units - simultaneous internal and external call speaker- phone speech decoder line line micro- loud- ssdi/iom ? -2 in out speaker phone line side acoustic side memory sci 0 0 0 channel 1 0 0 00 0 dtmf detector cpt decoder line echo canceller equalizer
psb 4860 functional description semiconductor group 27 10.97 2.1 functional units in this section the functional units of the psb 4860 are described in detail. the functional units can be individually enabled or disabled. 2.1.1 full duplex speakerphone the speakerphone unit (figure 10 ) is attached to four signals (microphone, loudspeaker, line out and line in). the two input signals (microphone, line in) are preceded by a signal summation point. figure 10 speakerphone - signal connections internally, this unit can be divided into an echo cancellation unit and an echo suppression unit (figure 11 ). the echo cancellation unit provides the attenuation g c while the echo suppression unit provides the attenuation g s . the total attenuation att of the speakerphone is therefore att=g c +g s . figure 11 speakerphone - block diagram the echo suppression unit can be enabled without the echo cancellation unit. if the echo cancellation unit is disabled, the echo suppression unit still provides speakerphone functionality, albeit only half duplex. as the echo cancellation must be disabled during recording or playback of speech data, this option allows for speakerphone operation speakerphone s 11 s 12 a c o u s t i c s i d e l i n e s i d e i 2 i 1 i 3 i 4 microphone loudspeaker line out line in echo cancellation line out microphone loudspeaker line in echo suppression g c g s
psb 4860 functional description semiconductor group 28 10.97 even if recording or playback is going on. the echo suppression unit is also used to provide additional attenuation if the echo cancellation unit cannot provide all of the required attenuation itself. 2.1.2 echo cancellation a simplified block diagram of the echo cancellation unit is shown in figure 12 . figure 12 echo cancellation unit - block diagram the echo cancellation unit consists of an finite impulse response filter (fir) that models the expected acoustic echo, an nlms based adaption unit and a control unit. the expected echo is subtracted from the actual input signal from the microphone. if the model is exact and the echo does not exceed the length of the filter then the echo can be completely cancelled. however, even if this ideal state can be achieved for one given moment the acoustic echo usually changes over time. therefore the nlms unit continuously adapts the coefficients of the fir filter. this adaption process is steered by the control unit. as an example, the adaption is inhibited as long as double talk is detected by the control unit. furthermore the control unit informs the echo suppression unit about the achieved echo return loss. table 3 shows the registers associated with the echo cancellation unit. table 3 echo cancellation unit registers register # of bits name comment saelen 9 len length of fir filter saeatt 15 att attenuation reduction during double-talk saegs 3 gs global scale (all blocks) microphone loudspeaker - fir filter nlms control line out line in
psb 4860 functional description semiconductor group 29 10.97 the length of the fir filter can be varied from 127 to 511 taps (15.875ms to 63.875ms). the taps are grouped into blocks. each block contains 64 taps. the performance of the fir filter can be enhanced by prescaling some or call of the coefficients of the fir filter. a coefficient is prescaled by multiplying it by a constant. the advantage of prescaling is an enhanced precision and consequently an enhanced echo cancellation. the disadvantage is a reduced echo cancellation performance if the signal exceeds the maximal coefficient value. more precisely, if a coefficient at tap t i is scaled by a factor c i then the level of the echo (room impulse response) must not exceed max/ c i (max: maximum pcm value). as an example figure shows a typical room impulse response. figure 13 echo cancellation unit - typical room impulse response first of all, the echo never exceeds 0.5 of the maximum value. furthermore the echo never exceeds 0.25 of the maximum value after time t 0.25 . therefore all coefficients can be scaled by a factor of 2 and all coefficients for taps corresponding to times after t 0.25 can be scaled a factor of 4. the echo cancellation unit provides three parameters for scaling coefficients. the first parameter (gs) determines a scale for all coefficients. the second parameter (fb) determines the first block for which an additional scale (ps) takes effect. this feature can be used for different default settings like large or small rooms. saeps1 3 as partial scale (for blocks >= saeps2:fb) saeps2 3 fb first block affected by partial scale table 3 echo cancellation unit registers t a 0.5 0.25 t 0.25
psb 4860 functional description semiconductor group 30 10.97 2.1.3 echo suppression the echo suppression unit can be in one of three states: ? transmit state ? receive state ? idle state in transmit state the microphone signal drives the line output while the line input is attenuated. in receive state the loudspeaker signal is driven by the line input while the microphone signal is attenuated. in idle state both signal paths are active with evenly distributed attenuation. figure 14 echo suppression unit - states of operation line out line in microphone loudspeaker idle state line out line in microphone loudspeaker receive state line out line in microphone loudspeaker transmit state
psb 4860 functional description semiconductor group 31 10.97 figure 15 shows the signal flow graph of the echo suppression unit in more detail. figure 15 echo suppression unit - signal flow graph state switching is controlled by the speech comparators (scas, scls) and the speech detectors (sdx, sdr). the amplifiers (agcx, agcr, lgax, lgar) are used to achieve proper signal levels for each state. all blocks are programmable. thus the telephone set can be optimized and adjusted to the particular geometrical and acoustical environment. the following sections discuss each block of the echo suppression unit in detail. scls scas sdx sdr agcr agcx attenuation control line out microphone loudspeaker lgax lgar line in ghx ghr
psb 4860 functional description semiconductor group 32 10.97 2.1.3.1 speech detector for each signal source a speech detector (sdx, sdr) is available. the speech detectors are identical but can be programmed individually. figure 16 shows the signal flow graph of a speech detector. figure 16 speech detector - signal flow graph the first three units (lim, lp1, pd) are used for preprocessing the signal while the actual speech detection is performed by the background noise monitor. background noise monitor the tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. therefore the background noise monitor consists of the low-pass filter 2 (lp2) and the offset in two separate branches. basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). in contrast, background noise can be regarded approximately stationary from its average power. low-pass filter 2 provides different time constants for noise (non-detected speech) and speech. it determines the average of the noise reference level. in case of background noise the level at the output of lp2 is approximately the level of the input. as in the other branch an additional offset off is added to the signal, the comparator signals noise. at speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the lp2-branch. if the difference exceeds the offset off, the lim lp1 pd lp2 off lp1 pds pdn lp2s lp2n lp2l background noise monitor signal preprocessing - lim
psb 4860 functional description semiconductor group 33 10.97 comparator signals speech. therefore the output of the background noise monitor is a digital signal indicating speech (1) or noise (0). a small fade constant (lp2n) enables fast settling of lp2 to the average noise level after the end of speech recognition. however, a too small time constant for lp2n can cause rapid charging to such a high level that after recognizing speech the danger of an unwanted switching back to noise exists. it is recommended to choose a large rising constant (lp2s) so that speech itself charges the lp2 very slowly. generally, it is not recommended to choose an infinite lp2s because then approaching the noise level is disabled. during continuous speech or tones the lp2 will be charged until the limitation lp2l is reached. then the value of lp2 is frozen until a break discharges the lp2. this limitation permits transmission of continuous tones and music on hold. the offset stage represents the estimated difference between the speech signal and averaged noise. signal preprocessing as described in the preceding chapter, the background noise monitor is able to discriminate between speech and noise. in very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. therefore a peak detection is required in front of the noise monitor. the main task of the peak detector (pd) is to bridge the very short speech pauses during a monolog so that this time constant has to be long. furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. but if no speech is recognized the noise low-pass lp2 must be charged faster to the average noise level. in addition, the noise edges are to be smoothed. therefore two time constants are necessary. as the peak detector is very sensitive to spikes, the low-pass lp1 filters the incoming signal containing noise in a way that main spikes are eliminated. due to the programmable time constant it is possible to refuse high-energy sibilants and noise edges. to compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. the limitation of the logarithmic amplifier can be programmed via the parameter lim. lim is related to the maximum pcm level. a signal exceeding the limitation defined by lim is getting amplified logarithmically, while very smooth system noise below is neglected. it should be the level of the minimum system noise which is always existing; in the transmit path the noise generated by the telephone circuitry itself and in receive direction the level of the first bit which is stable without any speech signal at the receive path. table 6 shows the parameters for the speech detector.
psb 4860 functional description semiconductor group 34 10.97 the input signal of the speech detector can be connected to either the input signal of the echo suppression unit (as shown for sdx) or the output of the associated agc (as shown for sdr). table 4 speech detector parameters parameter # of bytes range comment lim 1 0 to 95 db limitation of log. amplifier off 1 0 to 95 db level offset up to detected noise pds 1 1 to 2000 ms peak decrement pd1 (speech) pdn 1 1 to 2000 ms peak decrement pd1 (noise) lp1 1 1 to 2000 ms time constant lp1 lp2s 1 2 to 250 s time constant lp2 (speech) lp2n 1 1 to 2000 ms time constant lp2 (noise) lp2l 1 0 to 95 db maximum value of lp2
psb 4860 functional description semiconductor group 35 10.97 2.1.3.2 speech comparators (sc) the echo suppression unit has two identical speech comparators (scas, scls). each comparator can be programmed individually to accommodate the different system characteristics of the acoustic interface and the line interface. as scas and scls are identical, the following description holds for both scas and scls. the sc has two input signals sx and sr, which map to microphone/loudspeaker for scas and line in/line out for scls. in principle, the sc works according to the following equation: therefore, scas controls the switching to transmit state and scls controls the switching to receive state. switching is done only if sx exceeds sr by at least the expected acoustic level enhancement v which is divided into two parts: g and gd. a block diagram of the sc is shown in figure 17 . figure 17 speech comparator - block diagram at both inputs, logarithmic amplifiers compress the signal range. hence after the required signal processing for controlling the acoustic echo, pure logarithmic levels on both paths are compared. the main task of the comparator is to control the echo. the internal coupling due to the direct sound and mechanical resonances are covered by g. the external coupling, mainly caused by the acoustic feedback, is controlled by gd/pd. if sx > sr + v then switch state g gds gdn pds pdn sx sr log. amp. base gain gain reserve peak decrement log. amp. pds pdn peak decrement
psb 4860 functional description semiconductor group 36 10.97 the base gain (g) corresponds to the terminal couplings of the complete telephone: g is the measured or calculated level enhancement between both receive and transmit inputs of the sc. to control the acoustic feedback two parameters are necessary: gd represents the actual reserve on the measured g. together with the peak decrement (pd) it simulates the echo behavior at the acoustic side: after speech has ended there is a short time during which hard couplings through the mechanics and resonances and the direct echo are present. till the end of that time ( d t ) the level enhancement v must be at least equal to g to prevent clipping caused by these internal couplings. then, only the acoustic feedback is present. this coupling, however, is reduced by air attenuation. for this in general the longer the delay, the smaller the echo being valid. this echo behavior is featured by the decrement pd. figure 18 speech comparator - interdependence of parameters according to figure 18 , a compromise between the reserve gd and the decrement pd has to be made: a smaller reserve (gd) above the level enhancement g requires a longer time to decrease (pd). it is easy to overshout the other side but the intercommunication is harder because after the end of the speech, the level of the estimated echo has to be exceeded. in contrary, with a higher reserve (gd*) it is harder to overshout continuous speech or tones, but it enables a faster intercommunication because of a stronger decrement (pd*). t db d t gd* gd pd* pd rx-speech rx-noise g g
psb 4860 functional description semiconductor group 37 10.97 two pairs of coefficients, gds/pds when speech is detected, and gdn/pdn in case of noise, offer a different echo handling for speech and non-speech. with speech, even if very strong resonances are present, the performance will not be worsened by the high gds needed. only when speech is detected, a high reserve prevents clipping. a time period et [ms] after speech end, the parameters of the comparator are switched to the noise values. if both sets of the parameters are equal, et has no function. 2.1.3.3 attenuation control the attenuation control unit controls the attenuation stages ghx and ghr and performs state switching. the programmable attenuation att is completely switched to ghx (ghr) in receive state (transmit state). in idle state both ghx and ghr attenuate by att/2. in addition, attenuation is also influenced by the automatic gain control stages (agcx, agcr). state switching depends on the signals of one speech comparator and the corresponding speech detector. while each state is associated with the programmed attenuation, the time is takes to reach the steady-state attenuation after a state switch can be programmed (t sw ). if the current state is either transmit or receive and no speech on either side has been detected for time t w then idle state is entered. to smoothen the transition, the attenuation is incremented (decremented) by ds until the evenly distribution att/2 for both ghx and ghr is reached. table 6 shows the parameters for the attenuation unit. note that t sw is dependent on the current attenuation by the formula . table 5 speech comparator parameters parameter # of bytes range comment g 1 C 48 to + 48 db base gain gds 1 0 to 48 db gain reserve (speech) pds 1 0.025 to 6 db/ms peak decrement (speech) gdn 1 0 to 48 db gain reserve (noise) pdn 1 0.025 to 6 db/ms peak decrement (noise) et 1 0 to 992 ms time to switch from speech to noise parameters t sw sw att =
psb 4860 functional description semiconductor group 38 10.97 note: in addition, attenuation is also influenced by the automatic gain control stages (agcx, agcr) in order to keep the total loop attenuation constant. 2.1.3.4 echo suppression status output the psb 4860 can report the current state of the echo suppression unit to ease optimization of the parameter set of the echo suppression unit. in this case the sps 0 and sps 1 pins are set according to table 7 . furthermore the controller can read the current value of the sps pins by reading register spsctl. 2.1.3.5 loudhearing the speakerphone unit can also be used for controlled loudhearing. if enabled in loudhearing mode, the loudspeaker amplifier of the psb 4851 (als) is used instead of ghr (figure 15 ) when appropriate to avoid oscillation. in order to enable this feature, the psb 4851 must be programmed to allow als override. the als field within the afe control register afectl defines the value sent to the psb 4851 if attenuation is necessary (see specification of the psb 4851). 2.1.3.6 automatic gain control the echo suppression unit has two identical automatic gain control units (agcx, agcr). table 6 attenuation control unit parameters parameter # of bytes range comment tw 1 16 ms to 4 s t w to return to idle state att 1 0 to 95 db attenuation for ghx and ghr ds 1 0.6 to 680 ms/db decay speed (to idle state) sw 1 0.0052 to 10 ms/db decay rate (used for t sw ) table 7 sps output encoding sps 0 sps 1 echo suppression unit state 0 0 no echo suppression operation 0 1 receive 10transmit 1 1 idle
psb 4860 functional description semiconductor group 39 10.97 operation of the agc depends on a threshold level defined by the parameter com (value relative to the maximum pcm-value). the regulation speed is controlled by speedh for signal amplitudes above the threshold and speedl for amplitudes below. usually speedh will be chosen to be at least 10 times faster than speedl. the bold line in figure 19 depicts the steady-state output level of the agc as a function of the input level. figure 19 echo suppression unit - automatic gain control for reasons of physiological acceptance the agc gain is automatically reduced in case of continuous background noise (e.g. by ventilators). the reduction is programmed via the nols parameter. when the noise level exceeds the threshold determined by nois, the amplification will be reduced by the same amount the noise level is above the threshold. the current gain/attenuation of the agc can be read at any time (ag_cur). an additional low pass with time constant lp is provided to avoid an immediate response of the agc to very short signal bursts. if sdx detects noise, agcx is not working. in this case the last gain setting is used. regulation starts with this value as soon as sdx detects speech. likewise, if sdr detects noise, agcr is not working. in this case the last gain setting is used. regulation starts with this value as soon as sdr detects speech. when the agc has been disabled the initial gain used immediately after enabling the agc can be programmed. table 8 shows the parameters of the agc. com ag_att ag_gain agc input level agc output level max. pcm -10 db -20 db -10 db -20 db example: com ag_gain ag_att = = = -30 db 15 db 20 db
psb 4860 functional description semiconductor group 40 10.97 note: there are two sets of parameters, one for agcx and one for agcr. note: by setting ag_gain to 0 db a limitation function can be realized with the agc. 2.1.3.7 fixed gain each signal path features an additional amplifier (lgax, lgar) that can be set to a fixed gain. these amplifiers should be used for the basic amplification in order to avoid saturation in the preceding stages. table 9 shows the only parameter of this stage. 2.1.3.8 mode control table 10 shows the registers used to determine the signal sources and the mode. table 8 automatic gain control parameters parameter # of bytes range comment ag_init 1 -95 db to 95db initial agc gain/attenuation com 1 0 to C 95 db compare level rel. to max. pcm-value ag_att 1 0 to -95 db attenuation range ag_gain 1 0 to 95 db gain range ag_cur 1 -95 db to 95 db current gain/attenuation speedl 1 0.25 to 62.5 db/s change rate for lower levels speedh 1 0.25 to 62.5 db/s change rate for higher levels nois 1 0 to C 95 db threshold for agc-reduction by background noise lp 1 0.025 to 16 ms agc low pass time constant table 9 fixed gain parameters parameter # of bytes range comment lga 1 -12 db to 12 db always active table 10 speakerphone control registers register # of bits name comment sctl 1 ens echo suppression unit enable sctl 1 enc echo cancellation unit enable sctl 1 md speakerphone or loudhearing mode sctl 1 agx agcx enable
psb 4860 functional description semiconductor group 41 10.97 sctl 1 agr agcr enable sctl 1 sdx sdx input tap sctl 1 sdr sdr input tap afectl 4 als als value for loudhearing ssrc1 5 i1 input signal 1 (microphone) ssrc1 5 i2 input signal 2 (microphone) ssrc2 5 i3 input signal 3 (line in) ssrc2 5 i4 input signal 4 (line in) table 10 speakerphone control registers
psb 4860 functional description semiconductor group 42 10.97 2.1.4 line echo canceller the psb 4860 contains an adaptive line echo cancellation unit for the cancellation of near end echoes. the unit has two modes: normal and extended. in normal mode, the maximum echo length is 4 ms. this mode is always available. in extended mode, the maximum echo length is 24 ms. extended mode cannot be used while the speech encoder, the echo cancellation unit or slow playback is active. the line echo cancellation unit is especially useful in front of the various detectors (dtmf, cpt, etc.). a block diagram is shown in figure 20 . figure 20 line echo cancellation unit - block diagram the line echo canceller provides only one outgoing signal (s 15 ) as the other outgoing signal would be identical with the input signal i 1 . input i 2 is usually connected to the line input while input i 1 is connected to the outgoing signal. in normal mode the adaption process can be controlled by three parameters: min, att and mgn. adaption takes only place if both of the following conditions hold: 1. 2. with the first condition adaption to small signals can be avoided. the second condition avoids adaption during double talk. the parameter att represents the echo loss provided by external circuitry. the adaption stops if the power of the received signal (i2) exceeds the power of the expected signal (i1-att) by more than the margin mgn. + - s adaptive filter i 2 s 15 i 1 i1 min > i1 i2 Cattmgn + C0 >
psb 4860 functional description semiconductor group 43 10.97 table 11 shows the registers associated with the line echo canceller. table 11 line echo cancellation unit registers register # of bits name comment relevant mode lecctl 1 en line echo canceller enable both lecctl 1 md line echo canceller mode lecctl 5 i2 input signal selection for i 2 both lecctl 5 i1 input signal selection for i 1 both leclev 15 min minimal power for signal i 1 normal lecatt 15 att externally provided attenuation (i 1 to i 2 ) normal lecmgn 15 mgn margin for double talk detection normal
psb 4860 functional description semiconductor group 44 10.97 2.1.5 dtmf detector figure 21 shows a block diagram of the dtmf detector. the results of the detector are available in the status register and a dedicated result register that can be read via the serial control interface (sci) by the external controller. all sixteen standard dtmf tones are recognized. figure 21 dtmf detector - block diagram table 12 to 14 show the associated registers. as soon as a valid dtmf tone is recognized, the status word and the dtmf tone code are updated (table 13 ). dtv is set when a dtmf tone is recognized and reset when no dtmf tone is recognized or the detector is disabled. the code for the dtmf tone is placed into the register ddctl. the registers ddtw and ddlev hold parameters for detection (table 14 ). table 12 dtmf detector control register register # of bits name comment ddctl 1 en dtmf detector enable ddctl 5 i1 input signal selection table 13 dtmf detector results register # of bits name comment status 1 dtv dtmf code valid ddctl 5 dtc dtmf tone code table 14 dtmf detector parameters register # of bits name comment ddtw 15 twist twist for dtmf recognition ddlev 6 min minimum signal level to detect dtmf tones dtmf sci i 1 recognition
psb 4860 functional description semiconductor group 45 10.97 2.1.6 cng detector the calling tone (cng) detector can detect the standard calling tones of fax machines or modems. this helps to distinguish voice messages from data transfers. the result of the detector is available in the status register that can be read via the serial control interface (sci) by the external controller. the cng detector consists of two band-pass filters with fixed center frequency of 1100 hz and 1300 hz. figure 22 cng detector - block diagram table 15 shows the available parameters. both the programmed minimum time and the minimum signal level must be exceeded for a valid cng tone. furthermore the input signal resolution can be reduced by the res parameter. this can be useful in a noisy environment at low signal levels although the accuracy of the detection decreases. as soon as a valid tone is recognized, the status word of the psb 4860 is updated. the status bits are defined as follows: table 15 cng detector registers register # of bits name comment cngctl 1 en cng detector enable cngctl 5 i1 input signal selection cnglev 16 min minimum signal level cngbt 16 time minimum time of signal burst cngres 16 res input signal resolution table 16 cng detector result register # of bits name comment status 1 cng fax/modem calling tone detected cng detector sci i 1 1100 hz 1300 hz
psb 4860 functional description semiconductor group 46 10.97 2.1.7 alert tone detector the alert tone detector can detect the standard alert tones (2130 hz and 2750 hz) for caller id protocols. the results of the detector are available in the status register and the dedicated register atdctl0 that can be read via the serial control interface (sci) by the external controller. figure 23 alert tone detector - block diagram as soon as a valid alert tone is recognized, the status word of the psb 4860 and the code for the detected combination of alert tones are updated (table 18 ). table 17 alert tone detector registers register # of bits name comment atdctl0 1 en alert tone detector enable atdctl0 5 i1 input signal selection atdctl1 1 md detection of dual tones or single tones atdctl1 1 dev maximum deviation (0.5% or 1.1%) atdctl1 8 min minimum signal level to detect alert tones table 18 alert tone detector results register # of bits name comment status 1 atv alert tone detected atdctl0 2 atc alert tone code alert tone sci i 1 detector
psb 4860 functional description semiconductor group 47 10.97 2.1.8 cpt detector the selected signal is monitored continuously for a call progress tone. the cpt detector consists of a band-pass and an optional timing checker (figure 24 ). figure 24 cpt detector - block diagram the cpt detector can be used in two modes: raw and cooked. in raw mode, the occurrence of a signal within the frequency range, time and energy limits is directly reported. the timing checker is bypassed and therefore the psb 4860 does not interpret the length or interval of the signal. in cooked mode, the number and duration of signal bursts are interpreted by the timing checker. a signal burst followed by a gap is called a cycle. cooked mode requires a minimum of two cycles. the cpt flag is set with the first burst after the programmed number of cycles has been detected. the cpt flag remains set until the unit is disabled, even if the conditions are not met anymore. in this mode the cpt is modelled as a sequence of identical bursts separated by gaps with identical length. the psb 4860 can be programmed to accept a range for both the burst and the gap. it is also possible to specify a maximum aberration of two consecutive bursts and gaps. figure 25 shows the parameters for a single cycle (burst and gap). figure 25 cpt detector - cooked mode the status bit is defined as follows: timing band-pass sci (status) i 1 300-640 hz checker t bmax t bmin t gmin t gmax
psb 4860 functional description semiconductor group 48 10.97 cpt is not affected by reading the status word. it is automatically reset when the unit is disabled. table 20 shows the control register for the cpt detector. if any condition is violated during a sequence of cycles the timing checker is reset and restarts with the next valid burst. note: in cooked mode cpt is set with the first burst after the programmed number of cycles has been detected. note: the number of cycles must be set to zero in raw mode. table 19 cpt detector result register # of bits name comment status 1 cpt cp tone currently detected [340 hz; 640 hz] table 20 cpt detector registers register # of bits name comment cptctl 1 en unit enable cptctl 1 md mode (cooked, raw) cptctl 5 i1 input signal selection cptmn 8 minb minimum time of a signal burst (t bmin ) cptmn 8 ming minimum time of a signal gap (t gmin ) cptmx 8 maxb maximum time of a signal burst (t bmax ) cptmx 8 maxg maximum time of a signal gap (t gmax ) cptdt 8 difb maximum difference between consecutive bursts cptdt 8 difg maximum difference between consecutive gaps cpttr 3 num number of cycles (cooked mode), 0 (raw mode) cpttr 8 min minimum signal level to detect tones cpttr 4 sn minimal signal-to-noise ratio
psb 4860 functional description semiconductor group 49 10.97 2.1.9 caller id decoder the caller id decoder is basically a 1200 baud modem (fsk, demodulation only). the bit stream is formatted by a subsequent uart and the data is available in a data register along with status information (figure 26 ). figure 26 caller id decoder - block diagram the fsk demodulator supports two modes according to table 21 . the appropriate mode is detected automatically. the cid decoder does not interpret the data received. each byte received is placed into the cidctl register (table 23 ). the status byte of the psb 4860 is updated (table 22 ). cia and cd are cleared when the unit is disabled. in addition, cia is cleared when cidctl0 is read. table 21 caller id decoder modes mode mark (hz) space (hz) comment 1 1200 2200 bellcore 2 1300 2100 v.23 table 22 caller id decoder status register # of bits name comment status 1 cia cid byte received status 1 cd carrier detected table 23 caller id decoder registers register # of bits name comment cidctl0 1 en unit enable cidctl0 5 i1 input signal selection cidctl0 8 data last cid data byte received uart fsk demod. sci (status, data) i 1 (bellcore, v.23)
psb 4860 functional description semiconductor group 50 10.97 when the cid unit is enabled, it first waits for a channel seizure signal consisting of a series of alternating space and mark signals. the number of spaces and marks that have to be received without errors before the psb 4860 reports a carrier detect by setting status bit cd can be programmed. channel seizure must be followed by at least 16 continuous mark signals. the first space signal detected is then regarded as the start bit of the first message byte. the interpretation of the data, including message type, length and checksum is completely left to the controller. the cid unit should be disabled as soon as the complete information has been received as it cannot detect the end of the transmission by itself. note: some caller id mechanism may require additional external components for dc decoupling. these tasks must be handled by the controller. note: the controller is responsible for selecting and storing parts of the cid as needed. cidctl1 5 nmss number of mark/space sequences necessary for successful detection of carrier detect cidctl1 6 nmb number of mark bits necessary before space of first byte after carrier detect cidctl1 5 min minimum signal level for cid detection table 23 caller id decoder registers register # of bits name comment
psb 4860 functional description semiconductor group 51 10.97 2.1.10 dtmf generator the dtmf generator can generate single or dual tones with programmable frequency and gain. this unit is primarily used to generate the common dtmf tones but can also be used for signalling or other user defined tones. a block diagram is shown in figure 27 . figure 27 dtmf generator - block diagram both generators and amplifiers are identical. there are two modes for programming the generators, cooked mode and raw mode. in cooked mode, the standard dtmf frequencies are generated by programming a single 4 bit code. in raw mode, the frequency of each generator/amplifier can be programmed individually by a separate register. the unit has two outputs which provide the same signal but with individually programmable attenuation. table 24 shows the parameters of this unit. note: dgf1 and dgf2 are undefined when cooked mode is used and must not be written. table 24 dtmf generator registers register # of bits name comment dgctl 1 en enable for generators dgctl 1 md mode (cooked/raw) dgctl 4 dtc dtmf code (cooked mode) dgf1 15 frq1 frequency of generator 1 dgf2 15 frq2 frequency of generator 2 dgl 7 lev1 level of signal for generator 1 dgl 7 lev2 level of signal for generator 2 dgatt 8 att1 attenuation of s 9 dgatt 8 att2 attenuation of s 10 f 1 f 2 generator generator gain1 gain2 att2 s 9 s 10 att1
psb 4860 functional description semiconductor group 52 10.97 2.1.11 speech coder the speech coder (figure 28 ) has two input signals i 1 and i 2 . the first signal (i 1 ) is fed to the coder while the second signal (i2) is used as a reference signal for voice controlled recording. the signal i 1 can be coded by either a high quality coder or a long play coder. figure 28 speech coder - block diagram in high quality the output data stream runs at a fixed rate of 10300 bit/s and provides excellent speech quality. in long play mode, the output data stream is further reduced to an average of 3300 bit/s while still maintaining good quality. data is written starting at the current file pointer and the file pointer is advanced as needed. in case of any memory error (e.g. memory full) a file error is indicated and the coder is disabled. the controller must subsequently close the file. the coder can be switched on the fly. however, it may take up to 60 ms until the switch is executed. the controller must therefore wait for at least this time until issuing another command that relies on the mode switch. no audio data is lost during switching. the signal i 2 is first filtered by a low pass lp1 with programmable time constant and then compared to a reference level min. if the filtered signal exceeds min, then the status bit sd (table 25 ) is set immediately. if the filtered signal has been smaller than min for a programmable time time then the status bit sd is reset. the coder can be enabled in permanent mode or in voice recognition mode. in permanent mode, the coder starts immediately and compresses all input data continuously. the current state of the status bit sd does not affect the coder. in voice recognition mode, the coder is automatically started on the first transition of the status bit from 0 to 1. once the coder has started it remains active until disabled. table 25 speech coder status register # of bits name comment status 1 sd speech detected hq 10300 bit/s lp 3300 bit/s i 2 i 1 memory min lp
psb 4860 functional description semiconductor group 53 10.97 the operation of the speech coder is defined according to table 26 . note: the peak data rate in lp mode is 4800 bit/s. note: both hq and lp mode will not produce identical bit streams after a coding/ decoding cycle. table 26 speech coder registers register # of bits name comment scctl 1 en enable speech coder scctl 1 hq high quality mode scctl 1 vc voice controlled recording scctl 5 i1 input signal 1 selection scctl 5 i2 input signal 2 selection scct2 8 min minimal signal level for speech detection scct2 8 time minimum time for reset of sd scct3 8 lp time constant for low-pass
psb 4860 functional description semiconductor group 54 10.97 2.1.12 speech decoder the speech decoder (figure 29 ) decompresses the data previously coded by the speech coder unit and delivers a standard 128 kbit/s data stream. figure 29 speech decoder - block diagram the decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent of the selected quality. the decoder requests input data as needed at a variable rate. table 27 shows the signal and mode selection for the speech decoder. data reading starts at the location of the current file pointer. the file pointer is updated during speech decoding. if the end of the file is reached, the decoder is automatically disabled. the psb 4860 automatically resets sdctl:en at this point. table 27 speech decoder registers register # of bits name comment sdctl 1 en enable speech decoder sdctl 2 speed selection of playback speed hq 10300 bit/s lp 3300 bit/s s 13 memory
psb 4860 functional description semiconductor group 55 10.97 2.1.13 analog front end interface there are two identical interfaces at the analog side (to psb 4851) as shown in figure 30 . figure 30 analog front end interface - block diagram for each signal an amplifier is provided for level adjustment. the incoming signals can be passed through an optional high-pass (hp). this high-pass (f g =20 hz) is useful for blocking dc offsets and should be enabled by default. furthermore, up to three signals can be mixed in order to generate the outgoing signals (s 2 ,s 4 ). table 28 shows the associated registers. table 28 analog front end interface registers register # of bits name comment ifg1 16 ig1 gain for ig1 ifg2 16 ig2 gain for ig2 ifs1 1 hp high-pass for s 1 ifs1 5 i1 input signal 1 for ig2 ifs1 5 i2 input signal 2 for ig2 ifs1 5 i3 input signal 3 for ig2 ifg3 16 ig3 gain for ig3 ifg4 16 ig4 gain for ig4 ifs2 1 hp high-pass for s 3 ifs2 5 i1 input signal 1 for ig4 ifs2 5 i2 input signal 2 for ig4 ifs2 5 i3 input signal 3 for ig4 channel 2 s 1 channel 1 s 2 i 1 i 2 i 3 line out line in ig1 ig2 s 3 s 4 i 1 i 2 i 3 loudspeaker microphone ig4 hp ig3 hp
psb 4860 functional description semiconductor group 56 10.97 2.1.14 digital interface there are two almost identical interfaces at the digital side as shown in figure 31 . the only difference between these two interfaces is that only channel 1 supports the ssdi mode. figure 31 digital interface - block diagram each outgoing signal can be the sum of two signals with no attenuation and one signal with programmable attenuation (att). the attenuator can be used for artificial echo if there is none externally provided (e.g. isdn application). each input can be passed through an optional high-pass (hp). the associated registers are shown in table 29 . table 29 digital interface registers register # of bits name comment ifs3 5 i1 input signal 1 for s 6 ifs3 5 i2 input signal 2 for s 6 ifs3 5 i3 input signal 3 for s 6 ifs3 1 hp high-pass for s 5 ifs4 5 i1 input signal 1 for s 8 ifs4 5 i2 input signal 2 for s 8 ifs4 5 i3 input signal 3 for s 8 ifs4 1 hp high-pass for s 7 channel 2 (iom ? -2 interface) channel 1 (ssdi/iom ? -2 interface) s 7 s 8 i 1 i 2 i 3 att2 hp s 5 s 6 i 1 i 2 i 3 att1 hp
psb 4860 functional description semiconductor group 57 10.97 ifg5 8 att1 attenuation for input signal i3 (channel 1) ifg5 8 att2 attenuation for input signal i3 (channel 2) table 29 digital interface registers register # of bits name comment
psb 4860 functional description semiconductor group 58 10.97 2.1.15 universal attenuator the psb 4860 contains an universal attenuator that can be connected to any signal (e.g. for sidetone gain in isdn applications). figure 32 universal attenuator - block diagram table 30 shows the associated register. table 30 universal attenuator registers register # of bits name comment ua 8 att attenuation for ua ua 5 i1 input signal for ua s 14 ua i 1
psb 4860 functional description semiconductor group 59 10.97 2.1.16 automatic gain control unit in addition to the universal attenuator with programmable but fixed gain the psb 4860 contains an amplifier with automatic gain control (agc). the agc is preceeded by a signal summation point for two input signals. one of the input signals can be attenuated. figure 33 automatic gain control unit - block diagram furthermore the signal after the summation point is available. besides providing a general signal summation (s 16 not used) this signal is especially useful if the agc unit provides the input signal for the speech coder. in this case s 17 can be used as a reference signal for voice controlled recording. the operation of the agc is similar to agcx (accr) of the speakerphone. the differences are as follows: ? no nois parameter ? separate enable/disable control ? slightly different coefficient format furthermore the agc contains a comparator that starts and stops the gain regulation. the signal after the summation point (s17) is filtered by a peak detector with time constant dec for decay. then the signal is compared to a programmable limit lim. regulation takes only place when the filtered signal exceeds the limit. table 31 shows the associated registers. table 31 automatic gain control registers register # of bits name comment agcctl 1 en enable agcctl 5 i1 input signal 1 for agc agcctl 5 i2 input signal 2 for agc agcatt 15 att attenuation for i 2 agc1 8 ag_init initial agc gain/attenuation agc1 8 com compare level rel. to max. pcm-value s 16 agc i 1 att i 2 s 17
psb 4860 functional description semiconductor group 60 10.97 agc2 8 speedl change rate for lower levels agc2 8 speedh change rate for higher level agc3 8 ag_att attenuation range agc3 7 ag_gain gain range agc4 7 dec peak detector time constant agc4 8 lim comparator minimal signal level agc5 7 lp agc low pass time constant table 31 automatic gain control registers register # of bits name comment
psb 4860 functional description semiconductor group 61 10.97 2.1.17 equalizer the psb 4860 also provides an equalizer that can be inserted into any signal path. the main application for the equalizer is the adaption to the frequency characteristics of the microphone, transducer or loudspeaker. the equalizer consists of an iir filter followed by an fir filter as shown in figure 34 . figure 34 equalizer - block diagram the coefficients a 1 -a 9 , b 2 -b 9 and c 1 belong to the iir filter, the coefficients d 1- d 17 and c 2 belong to the fir filter. table 32 shows the registers associated with the equalizer. table 32 equalizer registers register # of bits name comment fcfctl 1 en enable fcfctl 5 i input signal for equalizer fcfctl 6 adr filter coefficient address fcfcof 16 filter coefficient data z -1 z -1 z -1 a1 a2 a9 z -1 z -1 z -1 c1 b2 b9 z -1 z -1 z -1 d1 d2 d17 c2 s 18 i fir iir
psb 4860 functional description semiconductor group 62 10.97 due to the multitude of coefficients the uses an indirect addressing scheme for reading or writing an individual coefficient. the address of the coefficient is given by adr and the actual value is read or written to register fcfcof. in order to ease programming the psb 4860 automatically increments the address adr after each access to fcfcof. note: any access to an out-of-range address automatically resets fcfctl:adr.
psb 4860 functional description semiconductor group 63 10.97 2.2 memory management memory management memory management - general this section describes the memory management provided by the psb 4860. as figure 35 shows, three units can access the external memory. during recording, the speech coder can write compressed speech data into the external memory. for playback, the speech decoder reads compressed speech data from external memory. in addition, the microcontroller can directly access the memory by the sci interface. figure 35 memory management - data flow the memory is organized as a file system. for each memory space (r/w-memory and voice prompt memory) the psb 4860 maintains a directory with 255 file descriptors (figure 36 ). figure 36 memory management - directory structure the directories must be created after each power failure for volatile r/w-memory. all file descriptors are cleared (all words zero). for non-volatile memory, the directories have to speech decoder speech coder memory sci length (0-65535) user data (16 bits) file descriptor 1 file descriptor 255 file descriptor n file descriptor (r/w) directory rtc1 (16 bits) rtc2 (16 bits)
psb 4860 functional description semiconductor group 64 10.97 be created only once. if the directories already exist, the memory has just to be activated after a reset. the file descriptors are not changed in this case. all commands that access the other fields or involve a write access must not be used in voice prompt memory space. 2.2.1 file definition and access a file is a linear sequence of units and can be accessed in two modes: binary and audio. in binary mode, a unit is a word. in audio mode, a unit is a variable number of words representing 30 ms of uncompressed speech. a file can contain at most 65535 units. figure 37 shows an audio file containing 100 audio units. the length of the message is therefore 3 s. figure 37 audio file organization - example figure 38 shows a binary file of 11 words containing a phonebook (with only two entries). figure 38 binary file organization - example there is one special file in the voice prompt directory (referenced by file number 255) which is intended for a large number of phrases and hence has a different organization.this file exists only in the directory for the voice prompt memory. it consists of up to 2048 phrases of arbitrary individual length. the actual number of units within an individual phrase is determined during creation and cannot be altered afterwards. phrases can be combined in any sequence without intermediate noise or gaps. hi jack, this is tom. please call me back tomorrow. 0 99 3 s 544f 4d20 3535 3534 3330 004a 4143 4b20 5555 5538 3131 to 010 1 m 555430 jack 555811
psb 4860 functional description semiconductor group 65 10.97 figure 39 shows a phrase file containing a total of five phrases. figure 39 phrase file organization - example before an access to a file can take place, the file must be opened with the following information: 1. memory space 2. file number 3. access mode these parameters remain effective until the next open command is given or, in case of the file pointer, until a file access. all other files are closed and cannot be accessed. the file with file number 0 is not a physical file. opening this file closes all physical files. the psb 4860 provides four registers for file access and two bits within the status register. table 33 shows these registers. the status register contains two flags (table 34 ) to indicate if currently a file command is under execution and if the last file command terminated without error. a new command must not be written to fcmd while the last one is still running (status:bsy=1). the only command that can be aborted is compress file. table 33 memory management registers register # of bits comment fcmd 16 command to execute fctl 16 access mode and file number fdata 16 data transfer and additional parameters fptr 16 (11) file pointer (phrase selector) status 16 busy and error indication table 34 memory management status register # of bits name comment status 1 bsy file command or decoder/encoder still running status 1 err file command completed/aborted with error one two you have messages left friday 01 4
psb 4860 functional description semiconductor group 66 10.97 writing to fcmd also resets the error bit in the status register. table 35 shows the parameters defining the access mode and the access location. all parameters can only be written when no file command is currently running. they become effective after the completion of an open command. if another unit (e.g. speech coder) accesses the file, the file pointer is updated automatically. therefore the controller can monitor the progress of recording or playing by reading the file pointer. commands are written to the fcmd register. the busy bit in the status register is set within 125 m s. the command may start execution after a delay, however (see section 2.2.5 ). some commands require additional parameters which are written prior to the command into the specified registers. data transfer is done by the register fdata (both reading and writing). 2.2.2 user data word the user data word consists of 12 bits that can be read or written by the user, two bits (r) that are reserved for future use and two read-only bits (d,m) which indicate the status of a file. if d is set, the file is marked for deletion and should not be used any more. this bit is maintained by the psb 4860 for housekeeping. table 35 memory management parameters register # of bits name comment fctl 1 ms memory space (r/w or voice prompt) fctl 1 md access mode (audio or binary) fctl 1 ts write timestamp (file open only) fctl 8 fno file number (active file) fptr 16 file pointer or phrase selector 15 0 d m r r user definable
psb 4860 functional description semiconductor group 67 10.97 2.2.3 high level memory management commands this section describes each of the high level memory management commands in detail. these commands are sufficient for normal operation of an answering machine. in addition, there are four low level commands (section 2.2.4 ). these commands are only required for special tasks like in-system reprogramming of the voice prompt area. memory management - commands 2.2.3.1 initialize this command creates a directory, sets the external memory configuration and delivers the size of usable memory in 1 kbyte blocks. furthermore the voice prompt memory space is scanned for a valid directory. the psb 4860 can either create an empty directory from scratch or leave the first n files of an existing directory untouched while deleting the remaining files (aram/dram only). this option is useful if due to an unexpected event (e.g. power loss during recording) some data is corrupted. in that case vital system information can still be recovered if it has been stored in the first files. possible errors: ? no r/w memory found ? more than 59 bad blocks (flash and aram) ? voice prompt directory requested, but not detected note: this command must be given only once for flash devices. table 36 initialize memory parameters register # of bits name comment fcmd 5 cmd initialize command code fcmd 1 in confirmation for initialization fctl 8 fno 0: delete no file 1: delete all files n: delete starting with file n cctl 2 mt type of r/w memory (dram, flash) cctl 1 mq quality of r/w memory (audio, normal) cctl 1 mv scan for voice prompt directory table 37 initialize memory results register # of bits name comment fdata 16 number of usable 1kbyte blocks in r/w memory
psb 4860 functional description semiconductor group 68 10.97 2.2.3.2 activate this command activates an existing directory, sets the external memory configuration and delivers the size of usable memory in 1 kbyte blocks. furthermore the voice prompt memory space is scanned for a valid directory. upon activation the psb 4860 checks (in case of aram/dram only) the consistency of the directory in r/w memory space. it returns the first file that contains corrupted data (if any). if corrupted data is detected an initialization should be performed with the same file number as an input parameter. possible error conditions: ? no memory connected ? no directory found ? device id wrong (flash only) ? corrupted files found (see fctl:fno) ? directory corrupted this command can have three types of result as shown in table 40 . table 38 activate memory parameters register # of bits name comment fcmd 5 cmd activate command code cctl 2 mt type of r/w memory (dram, flash) cctl 1 mq quality of r/w memory (audio, normal) cctl 1 mv voice prompt directory available table 39 activate memory results register # of bits name comment fdata 16 number of usable 1 kbyte blocks in r/w memory fctl 8 fno n: number of first corrupted file table 40 activate memory result interpretation result status: err fctl: fno comment no error 0 0 command successful, memory activated. soft error 1 n the first n-1 files are o.k. the memory is activated. hard error 1 1 the memory is not activated due to a hard error.
psb 4860 functional description semiconductor group 69 10.97 2.2.3.3 open file a specific file is opened for subsequent accesses with the specified access mode. opening a new file automatically closes the currently open file and clears the file pointer. opening file number 0 can be used to close all physical files. if the ts flag is set, the current content of rtc1 and rtc2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. possible error conditions: ? selected file marked for deletion, but not yet deleted by garbage collection ? memory space invalid ? new file selected, but memory full ? exceeds number of prompts (in voice prompt space only) ? wrong access mode selected for existing file note: in case of flash memory existing ones in the entries rtc1/rtc2 of the file descriptor cannot be altered. therefore ts should be set only once during the lifetime of a file. 2.2.3.4 open next free file the next free file is opened for subsequent write accesses with the specified access mode. the search starts at the specified file number. if the ts flag is set, the current content of rtc1 and rtc2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. if a free file has been found, the file is opened and the file number is returned in fctl:fno. otherwise an error is reported. table 41 open file parameters register # of bits name comment fcmd 5 cmd open command code fctl 1 ms memory space (r/w, voice prompt) fctl 1 md access mode (audio or binary) fctl 1 ts write timestamp fctl 8 fno file number table 42 open next free file parameters register # of bits name comment fcmd 5 cmd open next free file command code fctl 1 md access mode (audio or binary)
psb 4860 functional description semiconductor group 70 10.97 : possible error conditions: ? no unused file found ? memory full note: in case of flash memory existing ones cannot be altered. therefore ts should be set only once during the lifetime of a file. note: r/w-memory must be selected. otherwise the result is unpredictable. 2.2.3.5 seek the file pointer of the currently opened file is set to the specified position. if the current file is the phrase file the psb 4860 starts the speech decoder immediately after the seek is finished. this is done by simply enabling the decoder. all other settings of the decoder remain unaffected. the bsy bit is first set during the file command. it is then reset for a short period until the speech decoder is enabled internally. it is then set again while the decoder is running and finally reset when the phrase is finished. possible error conditions: ? file pointer out of range ? phrase number out of range fctl 1 ts write timestamp fctl 8 fno starting point (>0) table 43 open next free file results register # of bits name comment fctl 8 fno file number table 44 seek parameters register # of bits name comment fcmd 5 cmd seek command code fptr 16 (11) file pointer (phrase selector) table 42 open next free file parameters register # of bits name comment
psb 4860 functional description semiconductor group 71 10.97 2.2.3.6 cut file all units starting with the unit addressed by the file pointer are removed from the file. if all units are deleted the file is marked for deletion (see user data word). however, the associated file descriptor and memory space are released only after a subsequent garbage collection. possible error conditions: ? file pointer out of range ? voice prompt memory selected 2.2.3.7 compress file an audio file that has been recorded in hq mode can be recoded using lp mode. this reduces the file size to approximately one third of the original size. the speech quality, however, is somewhat lower compared to a signal that has been recorded in lp mode in the first place. this command can be aborted at any time and resumed later without loss of information. prior to this command all files must be closed. table 46 shows the parameters for this command. . possible error conditions: ? invalid ? another file currently open ? binary file selected table 45 cut file parameters register # of bits name comment fcmd 5 cmd cut command code fptr 16 position of first unit to delete table 46 compress file parameters register # of bits name comment fcmd 5 cmd compress command code fctl 8 fno file number
psb 4860 functional description semiconductor group 72 10.97 2.2.3.8 memory status this command returns the number of available 1 kb blocks in r/w memory space. possible error conditions: ? file open 2.2.3.9 garbage collection this command initiates a garbage collection. until a garbage collection files that are marked for deletion still occupy the associated file descriptor and memory space. after the garbage collection these file descriptors and the associated memory space are available again. this command can optionally remap the directory. in this mode the remaining file descriptors are remapped to form a contiguous block starting with file number 1. the original order is preserved. this command requires that all files are closed, i.e. file 0 is opened. independently of the selected directory only the read/write directory is used. possible error conditions: ? file open 2.2.3.10 access file descriptor by this command the length, user data word and rtc1/rtc2 of a file descriptor can be read. the user data word can also be written. the file or the other entries of the file descriptor are not affected by this command. table 47 memory status parameters register # of bits name comment fcmd 5 cmd memory status code table 48 memory status results register # of bits name comment fdata 16 free number of free blocks table 49 garbage collection parameters register # of bits name comment fcmd 5 cmd garbage collection command code fcmd 1 rd remap directory
psb 4860 functional description semiconductor group 73 10.97 possible error conditions: ? none note: in case of flash memory bits already set to 1 cannot be altered. note: do not use this command with the phrase file (fno = 255). 2.2.3.11 read data this command can be used in binary access mode only. a single word is read at the position given by the file pointer. the file pointer can be set by the seek command. the file pointer is advanced by one word automatically. possible error conditions: ? file pointer out of range ? phrase file selected ? audio file selected table 50 access file descriptor parameters register # of bits name comment fcmd 5 cmd read access or write access command code fdata 16 user data (write access only) table 51 access file descriptor results register # of bits name comment fdata 16 content of selected entry (read access only) table 52 read data parameters register # of bits name comment fcmd 5 cmd read data command code table 53 read data results register # of bits name comment fdata 16 data word
psb 4860 functional description semiconductor group 74 10.97 2.2.3.12 write data this commands can be used in binary access mode only. a single word is written at the position of the file pointer. the file pointer is advanced by one word automatically. note, that for flash memory only zeroes can be overwritten by ones. this restriction occurs only if an already used value within an existing file is to be overwritten. possible error conditions: ? file pointer out of range (for existing files only) ? voice prompt memory selected ? memory full ? audio file selected table 54 write data parameters register # of bits name comment fcmd 5 cmd access mode command code (including mode) fdata 16 data word
psb 4860 functional description semiconductor group 75 10.97 2.2.4 low level memory management commands these commands allow the direct access of any location (single word) of the external memory. additionally it is possible to erase any block in case of a flash device. these commands should not be used during normal operation as they may interfere with the file system. no file must be open when one of these commands is given. the primary use of these commands is the in-system programming of a flash device with voice prompts. please refer to the appropriate application notes. 2.2.4.1 set address this command sets the 24 bit address pointer aptr. only the address bits a 8 -a 23 are set, the address bits a 0 -a 7 are automatically cleared. possible error conditions: ? file open 2.2.4.2 dma read this command reads a single word addressed by aptr. after the read access aptr is automatically incremented by one. table 56 shows the parameters for this command. possible error conditions: ? file open table 55 set address parameters register # of bits name comment fcmd 5 cmd set address command code fdata 16 adr address bits a 8 -a 23 of address pointer aptr table 56 dma read parameters register # of bits name comment fcmd 5 cmd dma read command code table 57 dma read results register # of bits name comment fdata 16 data data read from address aptr.
psb 4860 functional description semiconductor group 76 10.97 2.2.4.3 dma write this command writes a single word to the location addressed by aptr. after the write access aptr is automatically incremented by one. table 58 shows the parameters for this command. possible error conditions: ? file open note: if flash memory is connected the actual write is only performed when the last word within a page is written. until then the data is merely buffered in the flash device. please check the flash memory data sheets on page size. 2.2.4.4 block erase this command erases the physical block which includes the address given by aptr. the actual amount of memory erased by this command depends on the block size of the flash device. table 59 shows the parameters for this command. possible error conditions: ? file open ? aram/dram configured table 58 dma write parameters register # of bits name comment fcmd 5 cmd dma write command code fdata 16 data data to be written to aptr table 59 block erase parameters register # of bits name comment fcmd 5 cmd block erase command code
psb 4860 functional description semiconductor group 77 10.97 2.2.5 execution time the execution time of the file commands is determined by four factors: 1. internal state of the psb 4860 2. memory configuration 3. memory state 4. individual characteristics of the memory devices therefore there is no general formula for an exact calculation of the execution time for file commands. for aram/dram items three and four are not significant as the memory access timing is always fixed and no additional delay is incurred for erasing memory blocks. however, the amount of memory has significant impact on the initialization in case of aram and flash. for flash devices the particular location of a write access in combination with the internal organization of the memory device may result in a block erase and subsequent write accesses in order to copy data. in this case the individual erase and write timing of the attached devices also prolongs the execution time. the first factor, the internal state of the psb 4860, can influence all file commands regardless of the memory type attached. in general the psb 4860 may delay any file command by up to 30 ms. however, it is possible to skip this delay if the following conditions hold: 1. the command is not initialize/activate 2. neither the dtmf detector nor the speech coder nor the speech decoder are running if neither condition is violated then the psb 4860 can be forced to start command execution immediately. this is done by setting the eie bit in the fcmd register along with the command code. table 60 gives an indication of the execution time for two typical memory configurations. table 60 execution times command aram (4 mbit) km29lv040 initialize 40 s 1) <11 s activate < 10 ms 3 s open file /open next free file <10 ms <26 ms seek (within 4 mbit file) <0.5 s <0.5 s seek (within phrase file) <1 ms <1 ms cut file <5 ms <5 ms compress file #units * 30 ms #units * 30 ms access file descriptor <10 ms <10 ms
psb 4860 functional description semiconductor group 78 10.97 2.2.6 special notes on file commands 1. no mmu commands must be inserted between opening a file and writing data to it, either by writing data to a binary file or by enabling the coder for audio files. therefore reading or writing the file descriptor is only allowed after all data writing has happened. 2. if an audio file has been opened for replay, a write file descriptor command must be followed by a seek command before the decoder can be enabled. 1) less than 20 ms for dram memory status <10 ms <10 ms read/write data <10 ms <10 ms garbage collection <20 ms 3 s table 60 execution times command aram (4 mbit) km29lv040
psb 4860 functional description semiconductor group 79 10.97 2.3 miscellaneous miscellaneous miscellaneous 2.3.1 real time clock the psb 4860 supplies a real time clock which maintains time with a resolution of a second and a range of up to a year. there are two registers which contain the current time and date (table 61 ). the real time clock maintains time during normal mode and power down mode only if the auxiliary oscillator osc is running and the rtc is enabled. note: writing out-of-range values to rtc1 and rtc2 results in undefined operation of the rtc 2.3.2 sps control register the two sps outputs (sps 0 , sps 1 ) can be used as either general purpose outputs, speakerphone status outputs, extended address outputs for voice prompt eprom or as status register outputs. table 62 shows the associated register. when used as status register outputs, the status register bit at position pos appears at sps 0 and the bit at position pos+1 appears at sps 1 . this mode of operation can be used for debugging purposes or direct polling of status register bits. 2.3.3 reset and power down mode the psb 4860 can be in either reset mode, power down mode or active mode. during reset the psb 4860 clears the hardware configuration registers and stops both internal table 61 real time clock registers register # of bits name comment rtc1 6 sec seconds elapsed rtc1 6 min minutes elapsed rtc2 5 hr hours elapsed rtc2 11 day days elapsed table 62 sps registers spsctl 1 sp0 output value of sps 0 spsctl 1 sp1 output value of sps 1 spsctl 3 mode mode of operation spsctl 4 pos position for status register window
psb 4860 functional description semiconductor group 80 10.97 and external activity. the address lines ma 0 -ma 15 provide a weak low until they are actually used as address lines (strong outputs) or auxiliary port pins (i/o). in reset mode the hardware configuration registers can be read and written. with the first access to a read/write register the psb 4860 enters active mode. in this mode the main oscillator is running and normal operation takes place. by setting the power down bit (pd) the psb 4860 can be brought to power down mode. in power down mode the main oscillator is stopped and, depending on hwconfig2:ppm), the memory control lines are released (weak high). depending on the configuration (aram/dram, app) the psb 4860 may still generate external activity (e.g. refresh cycles). the psb 4860 enters active mode again upon an access to a read/ write register. figure 40 shows a state chart of the modes of the psb 4860. figure 40 operation modes - state chart 2.3.4 interrupt the psb 4860 can generate an interrupt to inform the host of an update of the status register according to table 64 . an interrupt mask register (intm) can be used to disable or enable the interrupting capability of each bit of the status register except abt individually. table 63 power down bit register # of bits name comment cctl 1 pd power down mode reset active mode power down mode mode cctl.pd=1 r/w reg. access rst=1 rst=1 r/w reg. access
psb 4860 functional description semiconductor group 81 10.97 an interrupt is internally generated if any combination of these events occurs and the interrupt is not masked. the interrupt is cleared when the host reads the status register. if a new event occurs while the host reads the status register, the status register is updated after the current access is terminated and a new interrupt is generated immediately after the access has ended. note: if the internal interrupt occurs after the controller has already selected the device but not yet read the status word, then the status word is updated and the internal interrupt is cleared. therefore the controller should always evaluate the status word when read. 2.3.5 abort if the psb 4860 cannot continue the current operations in progress (e.g. due to a transient loss of power) it stops operation and initializes all read/write registers to their reset state. after that it sets the abt bit of the status register and generates an interrupt. the psb 4860 discards all commands with the exception of a write command to the revision register while abt is set. only after the write command to the revision register (with any value) the abt bit is reset and a reinitialization can take place. table 64 interrupt source summary status (old) status (new) set by reset by rdy=0 rdy=1 command completed command issued cia=0 cia=1 new caller id byte available cidctl0 read cd=0 cd=1 carrier detected carrier lost cd=1 cd=0 carrier lost carrier detected cpt=0 cpt=1 call progress tone detected cpt lost cpt=1 cpt=0 call progress tone lost cpt detected cng=0 cng=1 fax calling tone detected cng lost dtv=0 dtv=1 dtmf tone detected dtmf tone lost dtv=1 dtv=0 dtmf tone lost dtmf tone detected atv=0 atv=1 alert tone detected alert tone lost atv=1 atv=0 alert tone lost alert tone detected bsy=1 bsy=0 file command completed new command issued sd=0 sd=1 speech activity detected speech activity lost sd=1 sd=0 speech activity lost speech activity detected
psb 4860 functional description semiconductor group 82 10.97 2.3.6 revision register the psb 4860 contains a revision register. this register is read only and does not influence operation in any way. a write to the revision register clears the abt bit of the status register but does not alter the content of the revision register. 2.3.7 hardware configuration the psb 4860 can be adapted to various external hardware configurations by four special registers: hwconfig0 to hwconfig3. these registers are usually only written once during initialization and must not be changed while the psb 4860 is in active mode. it is mandatory that the programmed configuration reflects the external hardware for proper operation. special care must be taken to avoid i/o conflicts or excess current by enabling inputs without an external driving source. table 65 can be used as a checklist. 2.3.8 frame synchronization the psb 4860 locks itself to either an externally supplied clock or frame sync signal or generates the frame sync signal itself. this internal reference frame sync signal is called master frame sync (mfsc). in addition, the psb 4860 can derive the afeclk and afefsc from either the main oscillator or an auxiliary clock input. table 66 shows how afeclk and mfsc are derived by the psb 4860. the bits acs and mfs are contained in the hardware configuration registers. table 65 hardware configuration checklist register name value check hwconfig0 pfrdy 1 frdy must not float hwconfig0 osc 1 osc1/2 must be connected to a crystal hwconfig0 acs 1 clk must not float (tie low if no clock present) hwconfig1 mfs 1 fsc must not float (tie low if no clock present) hwconfig1 act 1 fsc must not float (tie low if no clock present) table 66 frame synchronization selection acs mfs afeclk mfsc application 0 0 xtal afefsc analog featurephone 0 1 - fsc isdn stand-alone 1 0 clk afefsc dect 1 1 clk fsc unused
psb 4860 functional description semiconductor group 83 10.97 2.3.9 clock tracking the psb 4860 can adjust afeclk and afefsc dynamically to a slightly varying fsc if afeclk and afefsc are derived from the main oscillator (xtal). this mode requires that both afefsc and fsc are nominally running at the same frequency (8 khz). this feature is especially useful when the fsc signal is not derived from the same clock source as afeclk (isdn application). 2.3.10 dependencies of modules there are some restrictions concerning the modules that can be enabled at the same time (table 67 ). a checked cell indicates that the two modules (defined by the row and the column of the cell) must not be enabled at the same time. there are three classes of file commands denoted by the letters b, o and i. table 68 shows the definition of these classes: examples: ? the line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder is running at slow speed. ? if the dtmf detector is running, none of the background file commands (b) must be executed. in addition, no file command must be executed with immediate execution 1) if speech decoder is running at slow speed table 67 dependencies of modules speech encoder speech decoder line ec (24 ms) acoustic ec dtmf detector file command speech enc. x x x b,o,i speech dec. x x 1) x b,o,i line ec (24 ms) x x 1) x b,o acoustic ec x x x x b,o dtmf det. x b,i file cmd. b,o,i b,o,i b,o b,o b,i table 68 file command classes class description b background commands (activate, recompress, garbage collection, initialize) o open commands (open, open next free file) i any command executed with eie=1 (i.e. immediate execution)
psb 4860 functional description semiconductor group 84 10.97 enabled (i). however, files my be opened and other commands (like read or write) may be executed without immediate execution enabled. furthermore it may be necessary to restrict the length of the fir filter of the echo cancellation unit if several other units are operating at the same time. the sum of all weights (table 69 ) of the simultaneously enabled modules must not exceed 100 at any given time. example: ? for an analog phone echo cancellation, dtmf tone generation, caller id reception, and line echo cancellation are necessary. the system uses the psb 4851 and the equalizer to linearize the loudspeaker. in this case the sum of all weights without echo cancellation is 35.6. therefore 255 taps can be used for a total of 98.1. ? in an isdn phone echo cancellation, channel 1 of the digital interface, the analog interface with clock tracking and the equalizer shall be enabled at the same time. in 1) the alert tone detector would add another 2.6, but can be disabled after the alert tone has been detected. therefore it can be left out of the calculation. table 69 module weights module weight comment example 1 example 2 equalizer 2.8 x x cpt detector 5.6 caller id decoder 1) 4.2 x cng detector 2.6 dtmf generator 2.2 x echo cancellation 52.1 127 taps (16 ms) echo cancellation 62.5 255 taps (32 ms) x echo cancellation 72.9 383 taps (48 ms) echo cancellation 83.3 511 taps (64 ms) x line echo cancellation 12.7 x universal attenuator 0.2 digital interface 1.7 channel 1 or ssdi x digital interface 1.7 channel 2 analog interface 2.5 x x clock tracking 0.6 x miscellaneous 8.0 always active x x
psb 4860 functional description semiconductor group 85 10.97 this application the sum of all weights without echo cancellation is 15.6. therefore 511 taps can be used for a total of 98.9.
psb 4860 functional description semiconductor group 86 10.97 2.4 interfaces interfaces interfaces this section describes the interfaces of the psb 4860. the psb 4860 supports both an iom ? -2 interface with single and double clock mode and a strobed serial data interface (ssdi). however, these two interfaces cannot be used simultaneously as they share some pins. both interfaces are for data transfer only and cannot be used for programming the psb 4860. table 70 lists the features of the two alternative interfaces. 2.4.1 iom ? -2 interface the data stream is partitioned into packets called frames. each frame is divided into a fixed number of timeslots. each timeslot is used to transfer 8 bits. figure 41 shows a commonly used terminal mode (three channels ch 0 , ch 1 and ch 2 with four timeslots each). the first timeslot (in figure 41 : b1) is denoted by number 0, the second one (b2) by 1 and so on. figure 41 iom ? -2 interface - frame structure the signal fsc is used to indicate the start of a frame. figure 42 shows as an example two valid fsc-signals (fsc, fsc * ) which both indicate the same clock cycle as the first clock cycle of a new frame (t 1 ). note: any timeslot (including m0, ci0, ...) can be used for data transfer. however, programming is not supported via the monitor channels. table 70 ssdi vs. iom ? -2 interface iom ? -2 ssdi signals 4 6 channels (bidirectional) 2 1 code linear pcm, a-law, m -law linear pcm synchronization within frame by timeslot (programmable) by signal (dxst, drst) b1 m0 b2 fsc dd/du ch 0 ch 1 ch 2 125 m s ci0 ic1 m1 ic2 ci1
psb 4860 functional description semiconductor group 87 10.97 figure 42 iom ? -2 interface - frame start the psb 4860 supports both single clock mode and double clock mode. in single clock mode, the bit rate is equal to the clock rate. bits are shifted out with the rising edge of dcl and sampled at the falling edge. in double clock mode, the clock runs at twice the bit rate. therefore for each bit there are two clock cycles. bits are shifted out with the rising edge of the first clock cycle and sampled with the falling edge of the second clock cycle. figure 43 shows the timing for single clock mode and figure 44 shows the timing for double clock mode. figure 43 iom ? -2 interface - single clock mode dcl fsc fsc * t 1 t 2 dcl t 1 t 2 dd/dr du/dx bit 0 bit 1 bit 2 bit 0 bit 1 bit 2
psb 4860 functional description semiconductor group 88 10.97 figure 44 iom ? -2 interface - double clock mode the psb 4860 supports up to two channels simultaneously for data transfer. both the coding (pcm or linear) and the data direction (dd/du assignment for transmit/receive) can be programmed individually for each channel. table 71 shows the registers used for configuration of the iom ? -2 interface. in a-law or m -law mode, only 8 bits are transferred and therefore only one timeslot is needed for a channel. in linear mode, 16 bits are needed for a single channel. in this mode, two consecutive timeslots are used for data transfer. bits 8 to 15 are transferred table 71 iom ? -2 interface registers register # of bits name comment sdconf 1 en interface enable sdconf 1 dcl selection of clock mode sdconf 6 nts number of timeslots within frame sdchn1 1 en channel 1 enable sdchn1 6 ts first timeslot (channel 1) sdchn1 1 dd data direction (channel 1) sdchn1 1 pcm 8 bit code or 16 bit linear pcm (channel 1) sdchn1 1 pcd 8 bit code (a-law or m -law, channel 1) sdchn2 1 en channel 2 enable sdchn2 6 ts first timeslot (channel 2) sdchn2 1 dd data direction (channel 2) sdchn2 1 pcm 8 bit code or 16 bit linear pcm (channel 2) sdchn2 1 pcd 8 bit code (a-law or m -law, channel 2) dcl t 1 dd/dr du/dx bit 0 bit 1 bit 2 bit 0 bit 1 t 2 t 3 t 4 t 5
psb 4860 functional description semiconductor group 89 10.97 within the first timeslot and bits 0 to 7 are transferred within the next timeslot. the first timeslot must have an even number. the most significant bit is always transmitted first.
psb 4860 functional description semiconductor group 90 10.97 2.4.2 ssdi interface the ssdi interface is intended for seamless connection to low-cost burst mode controllers (e.g. pmb 27251) and supports a single channel in each direction. the data stream is partitioned into frames. within each frame one 16 bit value can be sent and received by the psb 4860. the start of a frame is indicated by the rising edge of fsc. data is always sampled at the falling edge of dcl and shifted out with the rising edge of dcl. the ssdi transmitter and receiver are operating independently of each other except that both use the same fsc and dcl signal. 2.4.2.1 ssdi interface - transmitter the psb 4860 indicates outgoing data (on signal dx) by activating dxst for 16 clocks. the signal dxst is activated with the same rising edge of dcl that is used to send the first bit (bit 15) of the data. dxst is deactivated with the first rising edge of dcl after the last bit has been transferred. the psb 4860 drives the signal dx only when dxst is activated. figure 45 shows the timing for the transmitter. figure 45 ssdi interface - transmitter timing 2.4.2.2 ssdi interface - receiver valid data is indicated by an active drst pulse. each drst pulse must last for exactly 16 dcl clocks. as there may be more than one drst pulses within a single frame the psb 4860 can be programmed to listen to the n-th pulse with n ranging from 1 to 16. in order to detect the first pulse properly, drst must not be active at the rising edge of fsc. in figure 46 the psb 4860 is listening to the third drst pulse (n=3). fsc 125 m s dxst dcl du/dx bit 15 bit 14 bit 1 bit 0
psb 4860 functional description semiconductor group 91 10.97 figure 46 ssdi interface - active pulse selection figure 47 shows the timing for the ssdi receiver. figure 47 ssdi interface - receiver timing table 72 shows the registers used for configuration of the ssdi interface. table 72 ssdi interface register register # of bits name comment sdchn1 4 nas number of active drst strobe fsc drst active pulse (n=3) fsc 125 m s drst dcl dd/dr bit 15 bit 14 bit 1 bit 0
psb 4860 functional description semiconductor group 92 10.97 2.4.3 analog front end interface the psb 4860 uses a four wire interface similar to the iom ? -2 interface to exchange information with the analog front end (psb 4851). the main difference is that all timeslots and the channel assignments are fixed as shown in figure 48 . . figure 48 analog front end interface - frame structure voice data is transferred in 16 bit linear coding in two bidirectional channels c 1 and c 2 . an auxiliary channel c 3 is used to transfer the current setting of the loudspeaker amplifier als to the psb 4860. the remaining bits are fixed to zero. in the other direction c 3 transfers an override value for als from the psb 4860 to the psb 4851. an additional override bit ov determines if the currently transmitted value should override the aoar:lsc 1) setting. the aoar:lsc setting is not affected by c 3 :als override. table 73 shows the source control of the gain for the als amplifier. furthermore the afe interface can be enabled or disabled according to table 74 . 1) see specification of psb 4851, automatically set by the psb 4860 in loudhearing mode. table 73 control of als amplifier aopr:ovre c 3 :ov gain of als amplifier 0 - aoar:lsc 1 0 aoar:lsc 11c 3 :als table 74 analog front end interface register register # of bits name comment afectl 1 en interface enable channel c 1 channel c 3 channel c 2 afefs afedd 125 m s als afedu unused 000ov 16 bit 16 bit 8 bit
psb 4860 functional description semiconductor group 93 10.97 figure 49 analog front end interface - frame start figure 49 shows the synchronization of a frame by afefs. the first clock of a new frame (t 1 ) is indicated by afefs switching from low to high before the falling edge of t 1 . afefs may remain high during subsequent cycles up to t 32 . figure 50 analog front end interface - data transfer the data is shifted out with the rising edge of afeclk and sampled at the falling edge of afeclk (figure 50 ). if aopr:ovre is not set, the channel c 3 is not used by the psb 4851. all values (c 1 , c 2 , c 3 :als) are transferred msb first. the data clock (afeclk) rate is fixed at 6.912 mhz. table 75 shows the clock cycles used for the three channels. table 75analog front end interface clock cycles clock cycles afedd (driven by psb 4860) afedu (driven by psb 4851) t 1 -t 16 c 1 data c 1 data t 17 -t 32 c 2 data c 2 data t 33 -t 40 c 3 data c 3 data t 41 -t 864 0 tristate afeclk afefs t 1 t 2 afeclk t 1 t 2 afedd afedu bit 0 bit 1 bit 2 bit 0 bit 1 bit 2
psb 4860 functional description semiconductor group 94 10.97 2.4.4 serial control interface the serial control interface (sci) uses four lines: sdr, sdx, sclk and cs . data is transferred by the lines sdr and sdx at the rate given by sclk. the falling edge of cs indicates the beginning of an access. data is sampled by the psb 4860 at the rising edge of sclk and shifted out at the falling edge of sclk. each access must be terminated by a rising edge of cs . the accesses to the psb 4860 can be divided into three classes: 1. configuration read/write 2. status/data read 3. register read/write if the psb 4860 is in power down mode, a read access to the status register does not deliver valid data with the exception of the rdy bit. after the status has been read the access can be either terminated or extended to read data from the psb 4860. a register read/write access can only be performed when the psb 4860 is ready. the rdy bit in the status register provides this information. any access to the psb 4860 starts with the transfer of 16 bits to the psb 4860 over line sdr. this first word specifies the access class, access type (read or write) and, if necessary, the register accessed. if a configuration register is written, the first word also includes the data and the access is terminated. likewise, if a register read is issued, the access is terminated after the first word. all other accesses continue by the transfer of the status register from the psb 4860 over line sdx. if a register (excluding configuration) is to be written, the next 16 bits containing the data are transferred over line sdr and the access is terminated. figures 51 to 54 show the timing diagrams for the different access classes and types to the psb 4860. figure 51 status register read access cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for status register read : status register : int
psb 4860 functional description semiconductor group 95 10.97 figure 52 data read access figure 53 register write access cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for data read : status register : d 15 d 14 d 1 d 0 d 15 ,..,d 0 : data to be read : cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for register write : status register : d 15 d 14 d 1 d 0 d 15 ,..,d 0 : data to be written :
psb 4860 functional description semiconductor group 96 10.97 figure 54 configuration register read access configuration registers at even adresses use bit positions d 7 -d 0 while configuration registers at odd adresses use bit positions d 15 -d 8 . figure 55 configuration register write access or register read command the internal interrupt signal is cleared when the first bit of the status register is put on sdx. however, externally the signal int is deactivated as long as cs stays low. if the internal interrupt signal is not cleared or another event causing an interrupt occurs while the microcontroller is already reading the status belonging to the first event then int goes low again immediately after cs is removed. the timing is shown in figure 51 . table 76 shows the formats of the different command words. all other command words are reserved. cs sclk sdr c 15 c 14 c 1 c 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for configuration register read : status register : d 15 ,..,d 0 : data to be read : s 15 s 14 s 1 s 0 d 15 d 14 d 1 d 0 cs sclk sdr c 15 c 14 c 1 c 0 c 15 ,..,c 0 : command word for configuration register write : or register read :
psb 4860 functional description semiconductor group 97 10.97 in case of a configuration register write, w determines which configuration register is to be written (table 77 ): in case of a configuration register read, r determines which pair of configuration registers is to be read (table 78 ): note: reading any register except the status register or a hardware configuration register requires at least two accesses. the first access is a register read command (figure 55 ). with this access the register address is transferred to the. after that access data read accesses (figure 52 ) must be executed. the first data read access with status:rdy=1 delivers the value of the register. table 76 command words for register access 1514131211109876543210 read status register or data read access 0011000000000000 read register 0101 reg write register 0100 reg read configuration reg. 011100r000000000 write configuration reg. 011000 w data table 77 address field w for configuration register write 9 8 register 0 0 hwconfig 0 0 1 hwconfig 1 1 0 hwconfig 2 1 1 hwconfig 3 table 78 address field r for configuration register read 9 register pair 0 hwconfig 0 / hwconfig 1 1 hwconfig 2 / hwconfig 3
psb 4860 functional description semiconductor group 98 10.97 2.4.5 memory interface the psb 4860 supports either flash memory or aram/dram as external memory for storing messages. if aram/dram is used, an eprom can be added optionally to support read-only messages (e.g. voice prompts). table 79 summarizes the different configurations supported. if aram/dram is used, the total amount of memory must be a power of two and all devices must be of the same type. the pin frdy must be tied high. for flash devices, the psb 4860 supports in-circuit programming of voice prompts by releasing the control lines during reset and (optionally) power down. instead of actively driving the lines fcs , foe , fwe , fcle and ale these lines are pulled high by a weak pullup during reset and (optionally) power down. table 79 supported memory configurations mbit type bank 0 (d 0 -d 3 ) bank 1 (d 4 -d 7 ) comment 1 aram/dram 256kx4 - 2 aram/dram 256kx4 256kx4 4 aram/dram 1mx4 - 4 aram/dram 512kx8 8 aram/dram 1mx4 1mx4 16 aram/dram 4mx4 - 2k or 4k refresh 16 aram/dram 2mx8 2k refresh 32 aram/dram 4mx4 4mx4 2k or 4k refresh 32 aram/dram 2x2mx8 2k refresh 64 aram/dram 16mx4 - 4k or 8k refresh 64 aram/dram 8mx8 4k or 8k refresh 128 aram/dram 16mx4 16mx4 4k or 8k refresh 4-128 flash 512kx8 devices km29n040 16-128 flash 2mx8 devices km29n16000
psb 4860 functional description semiconductor group 99 10.97 2.4.5.1 aram/dram interface the psb 4860 supports up to two banks of memory which may be 4 bit or 8 bit wide (figure 56 ). if both banks are used they must be populated identically. figure 56 aram/dram interface - connection diagram ma 0 -ma 1 5 md 0 -md 3 ras cas 0 w a 0 -a 12 d 0 -d 3 ras cas w oe ma 0 -ma 1 5 md 0 -md 3 ras cas 0 w a 0 -a 12 d 0 -d 7 ras cas w oe single 4 bit bank single 8 bit bank ma 0 -ma 1 5 md 0 -md 7 ras cas 0 w a 0 -a 12 d 0 -d 3 ras cas w oe a 0 -a 12 d 0 -d 3 ras cas w oe md 4 -md 7 cas 1 two 4 bit banks ma 0 -ma 1 5 md 0 -md 7 ras cas 0 w a 0 -a 12 d 0 -d 7 ras cas w oe a 0 -a 12 d 0 -d 7 ras cas w oe cas 1 two 8 bit banks psb 4860 psb 4860 psb 4860 psb 4860
psb 4860 functional description semiconductor group 100 10.97 the psb 4860 also supports different internal organizations of aram/dram chips. table 80 shows the necessary connections on the address bus. the timing of the aram/dram interface is shown in figures 57 to 59 . the timing is derived form the internal memory clock mclk* which runs at a quarter of the system clock. figure 57 aram/dram interface - read cycle timing 1) see chip control register cctl table 80 address line usage (aram/dram mode) aram/dram cs9 1) ma 0 -ma 8 ma 9 ma 10 ma 11 ma 12 ma 13 256k x4 1 a 0 -a 8 512k x8 1 a 0 -a 8 a 9 1m x4 0 a 0 -a 8 a 9 4m x4 (2k refresh) 0 a 0 -a 8 a 9 a 10 4m x4 (4k refresh) 0 a 0 -a 8 a 9 a 10 a 11 2m x8 0 a 0 -a 8 a 9 a 10 16m x4 (4k refresh) 0 a 0 -a 8 a 9 a 10 a 11 16m x4 (8k refresh) 0 a 0 -a 8 a 9 a 10 a 11 a 12 8m x8 (4k refresh) 0 a 0 -a 8 a 9 a 10 a 11 8m x8 (8k refresh) 0 a 0 -a 8 a 9 a 10 a 11 a 12 mclk* ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr.
psb 4860 functional description semiconductor group 101 10.97 figure 58 aram/dram interface - write cycle timing figure 59 aram/dram interface - refresh cycle timing the psb 4860 ensures that ras remains inactive for at least one mclk*-cycle between successive accesses. the frequency at which refresh cycles are performed is shown in table 81 . 1) as programmed by hwconfig2:rsel table 81 refresh frequency selection refresh frequency comment 64 khz memory access (e.g. recording) in progress 8, 16, 32 or 64 khz 1) no memory access in progress or power-down mclk* ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr. w data out mclk* cas 0 ,cas 1 ras
psb 4860 functional description semiconductor group 102 10.97 2.4.5.2 eprom interface the psb 4860 supports an eprom in parallel with aram/dram. this interface is always 8 bits wide and supports a maximum of 256 kb. figure 60 shows a connection diagram and figure 61 the timing. this interface supports read cycles only. figure 60 eprom interface - connection diagram figure 61 eprom interface - read cycle timing note: in order to access more than 64 kb the pins sps 0 and sps 1 can be programmed to provide the address lines a 16 and a 17 . in this mode a 16 and a 17 remain stable during the whole read cycle. see the register spsctl for programming information. ma 0 -ma 1 5 md 0 -md 7 vprd a 0 -a 15 d 0 -d 7 ce oe psb 4860 a 16 a 17 sps 1 sps 0 vprd md 0 -md 7 mclk* ma 0 -ma 15
psb 4860 functional description semiconductor group 103 10.97 2.4.5.3 flash memory interface the psb 4860 has special support for the km29n040 and km29n16000 or equivalent devices. no external components are required for up to four km29n040. figure 62 shows the connection diagram for a single device. figure 62 flash memory interface - connection diagram table 82 shows the signals output during a device access on the ma-lines. the address bits can used by an external decoder. up to four km29n040 are supported directly by the decoded select signals fcs 0 -fcs 3 . table 82 address line usage (samsung mode) ma 11 ma 10 ma 9 ma 8 ma 7 ma 6 ma 5 ma 4 ma 3 ma 2 ma 1 ma 0 fcs 3 fcs 2 fcs 1 fcs 0 a 23 a 22 a 21 a 20 a 19 a 18 a 17 a 16 d 0 -d 7 ce re we cle md 0 -md 7 fcs foe fwr fcle ale ale +5v r/b frdy wp psb 4860
psb 4860 functional description semiconductor group 104 10.97 figure 63 shows an application with three km29n040 devices. figure 63 flash memory interface - multiple devices an access to the flash memory can consist of several partial access cycles where only the timing of the partial access cycles is defined but not the time between two adjacent partial access cycles. the psb 4860 performs three types of partial access cycles: 1. command write 2. address write 3. data read/write table 83 shows the supported accesses and the corresponding partial access cycles. table 83 flash memory command summary access command write address write 1 address write 2 address write 3 # of data read/write command write reset ff - - - - - status read 70 - - - 1 - block erase 60 a 8 -a 15 a 16 -a 23 --d0 read 00 a 0 -a 7 a 8 -a 15 a 16 -a 23 1-32 - write 80 a 0 -a7 a 8 -a 15 a 16 -a 23 1-32 10 d 0 -d 7 ce re we cle md 0 -md 7 foe fwr frdy ale ale +5v r/b fcle wp d 0 -d 7 ce re we cle ale r/b wp ma 8 ma 9 ma 10 d 0 -d 7 ce re we cle ale r/b wp psb 4860
psb 4860 functional description semiconductor group 105 10.97 the timing for the partial access cycles is shown in figures 64 to 65 . note that both fcs and ma 0 -ma 15 remain stable between the first and the last partial access of a device access. figure 64 flash memory interface - command write figure 65 flash memory interface - address write as there is no access that starts or stops with an address write cycle (figure 65 ) fcs is already low at the start of this cycle and also remains low. mclk* ma 0 -ma 11 md 0 -md 7 fwr fcs fcle data out mclk* md 0 -md 7 fwr ale data out address latch cycle t 0 t 1 t 2 t 3
psb 4860 functional description semiconductor group 106 10.97 figure 66 flash memory interface - data write as there is no access that starts or stops with a data write cycle (figure 66 ) fcs is already low at the start of this cycle and also remains low. figure 67 flash memory interface - data read if the device access ends with a read cycle, the fcs -signals go inactive after t 3 of the last read cycle. the data is latched at the rising edge of foe . mclk* md 0 -md 7 fwr data out write cycle t 0 t 1 t 2 t 3 mclk* md 0 -md 7 foe data in read cycle t 0 t 1 t 2 t 3
psb 4860 functional description semiconductor group 107 10.97 2.4.6 auxiliary parallel port the psb 4860 provides an auxiliary parallel port if the memory interface is in samsung mode and only one device is used. in this case the lines ma 0 to ma 15 are not needed for the memory interface and can therefore be used for an auxiliary parallel port. this port has two modes: static mode and multiplex mode. 2.4.6.1 static mode in static mode all pins of the auxiliary parallel port interface have identical functionality. any pin can be configured as an output or an input. pins configured as outputs provide a static signal as programmed by the controller. pins configured as inputs are monitoring the signal continuously without latching. the controller always reads the current value. table 84 shows the registers used for static mode. 2.4.6.2 multiplex mode in multiplex mode, the psb 4860 uses ma 12 -ma 15 to distinguish four timeslots. each timeslot has a duration of approximately 2 ms. the timeslots are separated by a gap of approximately 125 m s in which none of the signals at ma 12 -ma 15 are active. the psb 4860 multiplexes three more output registers to ma 0 -ma 11 in timeslots 0, 1 and 2. in timeslot 3 the direction of the pins can be programmed. for input pins, the signal is latched at the falling edge of ma 15 . table 85 shows the registers used for multiplex mode. this mode is useful for scanning keys or controlling seven segment led displays. table 84 static mode registers register # of bits comment dout3 16 output signals (for pins configured as outputs) din 16 input signals (for pins configured as inputs) ddir 16 pin direction table 85 multiplex mode registers register # of bits comment dout0 12 output signals on ma 0 -ma 11 while ma 15 =1 dout1 12 output signals on ma 0 -ma 11 while ma 14 =1 dout2 12 output signals on ma 0 -ma 11 while ma 13 =1 dout3 12 output signals (for pins configured as outputs) while ma 12 =1 din 12 input signals (for pins configured as inputs) at falling edge of ma 12 ddir 12 pin direction during ma 12 =1
psb 4860 functional description semiconductor group 108 10.97 figure 68 shows the timing diagram for multiplex mode. figure 68 auxiliary parallel port - multiplex mode note: in either mode the voltage at any pin (ma 0 to ma 15 ) must not exceed v dd. 2 ms ma 15 ma 14 ma 13 ma 12 ma 0 -ma 11 dout0 dout2 dout1 dout0 din/dout3
psb 4860 detailed register description semiconductor group 109 10.97 3 detailed register description the psb 4860 has a single status register (read only) and an array of data registers (read/write). the purpose of the status register is to inform the external microcontroller of important status changes of the psb 4860 and to provide a handshake mechanism for data register reading or writing. if the psb 4860 generates an interrupt, the status register contains the reason of the interrupt. 3.1 status register rdy ready 0: the last command (if any) is still in progress. 1: the last command has been executed. abt abort 0: no exception during operation 1: some exception other than reset caused the psb 4860 to abort any operation currently in progress. the external microcontroller should reinitialize the psb 4860 to ensure proper operation. the abt bit is cleared by writing any value to register rev. no other command is accepted by the psb 4860 while abt is set. cia caller id available 0: no new data for caller id 1: new caller id byte available cd carrier detect 0: no carrier detected 1: carrier detected 1) undefined 15 0 rdy abt 0 0 cia cd cpt cng sd err bsy dtv atv - 1) - 1) - 1)
psb 4860 detailed register description semiconductor group 110 10.97 cpt call progress tone 0: currently no call progress tone detected or pause detected (raw mode) 1: currently a call progress is detected cng fax calling tone 0: currently no fax calling tone detected 1: currently a fax calling tone is detected sd speech detected 0: no speech detected 1: speech signal at input of coder err error (file command) 0: no error 1: last file command resulted in an error bsy busy (file command) 0: file system idle 1: file system still busy (also set during encoding/decoding) dtv dtmf tone valid 0: no new dtmf code available 1: new dtmf code available in ddctl atv alert tone valid 0: no new alert tone code available 1: new alert tone code available in adctl0
psb 4860 detailed register description semiconductor group 111 10.97 3.2 hardware configuration registers hwconfig 0 - hardware configuration register 0 ppsdx push/pull for sdx 0: the sdx pin has open-drain characteristic 1: the sdx pin has push/pull characteristic ppint push/pull for int 0: the int pin has open-drain characteristic 1: the int pin has push/pull characteristic pfrdy pullup for frdy 0: the internal pullup resistor of pin frdy is enabled 1: the internal pullup resistor of frdy is disabled ppsdi push/pull for sdi interface 0: the du and dd pins have open-drain characteristic 1: the du and dd pins have push/pull characteristic osc enable auxiliary oscillator 0: the auxiliary oscillator (osc 1 , osc 2 ) is disabled 1: the auxiliary oscillator (osc 1 , osc 2 ) is enabled rtc enable real time clock 0: the real time clock is disabled 1: the real time clock (rtc) is enabled. acs afe clock source 0: afeclk is derived from the main oscillator 1: afeclk is derived from the clk input pd power down (read only) 0: the psb 4860 is in active mode 1: the psb 4860 is in power down mode 7 0 pd acs rtc osc ppsdi pfrdy ppint ppsdx
psb 4860 detailed register description semiconductor group 112 10.97 hwconfig 1 - hardware configuration register 1 app auxiliary parallel port act afe clock tracking 0: afeclk tracking disabled 1: afeclk tracking enabled ads afe double speed 0: 8 khz afefsc 1: 16 khz afefsc mfs master frame sync selection 0: afefsc 1: fsc xtal xtal frequency ssdi ssdi interface selection 0: iom ? -2 interface 1: ssdi interface 1) the factor p is needed to calculate the clock frequency at afeclk. 7 0 app act ads mfs xtal ssdi 7 6 description 0 0 normal (aram/dram, intel type flash, voice prompt eprom) 0 1 app static mode 1 0 app multiplex mode 1 1 reserved 2 1 factor p 1) description 0 0 reserved reserved 0 1 4.5 31.104 mhz 1 0 reserved reserved 1 1 reserved reserved
psb 4860 detailed register description semiconductor group 113 10.97 hwconfig 2 - hardware configuration register 2 ppm push/pull for memory interface (reset, power down) 0: the signals for the memory interface have push/pull characteristic 1: the signals for the memory interface have pullup/pulldown characteristic esdx edge select for dx 0: dx is transmitted with the rising edge of dcl 1: dx is transmitted with the falling edge of dcl esdr edge select for dr 0: dr is latched with the falling edge of dcl 1: dr is latched with the rising edge of dcl csel codec selection for afe interface 0: interface to psb 4851 1: interface to ak 4510 chs channel select (ak 4510 only) rsel refresh select 7 0 ppm esdx esdr csel chs rsel 3 2 description 0 0 left channel of ak 4510 0 1 right channel of ak4510 1 0 left and right channel 1 1 reserved 1 0 description 0 0 64 khz refresh frequency 0 1 32 khz refresh frequency 1 0 16 khz refresh frequency 1 1 8 khz refresh frequency
psb 4860 detailed register description semiconductor group 114 10.97 hwconfig 3 - hardware configuration register 3 7 0 00000000
psb 4860 detailed register description semiconductor group 115 10.97 3.3 read/write registers the following sections contains all read/write registers of the psb 4860. the register addresses are given as hexadecimal values. registers marked with an r are affected by reset or a wake up after power down. all other registers retain their previous value. no access must be made to addresses other than those associated with a read/write register. 3.3.1 register table address. name long name page 00h rev revision.............................................................................. 119 01h r cctl chip control ....................................................................... 120 02h r intm interrupt mask register ...................................................... 121 03h r afectl analog front end interface control.................................... 122 04h r ifs1 interface select 1 ............................................................... 123 05h r ifg1 interface gain 1.................................................................. 124 06h r ifg2 interface gain 2.................................................................. 125 07h r ifs2 interface select 2 ............................................................... 126 08h r ifg3 interface gain 3.................................................................. 127 09h r ifg4 interface gain 4.................................................................. 128 0ah r sdconf serial data interface configuration .................................... 129 0bh r sdchn1 serial data interface channel 1 ......................................... 130 0chr ifs3 interface select 3 ............................................................... 132 0dhr sdchn2 serial data interface channel 2 ......................................... 133 0eh r ifs4 interface select 4 ............................................................... 134 0fh r ifg5 interface gain 5.................................................................. 135 10h r ua universal attenuator........................................................... 136 11h r dgctl dtmf generator control.................................................... 137 12h dgf1 dtmf generator frequency 1 ........................................... 138 13h dgf2 dtmf generator frequency 2 ........................................... 139 14h dgl dtmf generator level....................................................... 140 15h dgatt dtmf generator attenuation ............................................. 141 16h r cngctl calling tone control........................................................... 142 17h cngbt cng burst time ................................................................. 143 18h cnglev cng minimal signal level ................................................. 144 19h cngres cng signal resolution ...................................................... 145 1ah r atdctl0 alert tone detection 0........................................................ 146 1bh atdctl1 alert tone detection 1........................................................ 147 1chr cidctl0 caller id control 0.............................................................. 148 1dh cidctl1 caller id control 1.............................................................. 149 20h r cptctl call progress tone control ................................................ 150 21h cpttr call progress tone thresholds.......................................... 151 22h cptmn cpt minimum times.......................................................... 152
psb 4860 detailed register description semiconductor group 116 10.97 23h cptmx cpt maximum times......................................................... 153 24h cptdt cpt delta times ................................................................ 154 25h r lecctl line echo cancellation control .......................................... 155 26h leclev minimal signal level for line echo cancellation ............... 156 27h lecatt externally provided attenuation ......................................... 157 28h lecmgn margin for double talk detection....................................... 158 29h r ddctl dtmf detector control ...................................................... 159 2ah ddtw dtmf detector signal twist .............................................. 160 2bh ddlev dtmf detector minimum signal level............................... 161 2eh r fcfctl equalizer control................................................................ 162 2fh fcfcof equalizer coefficient data.................................................. 164 30h r scctl speech coder control........................................................ 165 31h scct2 speech coder control 2..................................................... 166 32h scct3 speech coder control 3..................................................... 167 34h r sdctl speech decoder control .................................................... 168 38h r agcctl agc control ....................................................................... 169 39h r agcatt automatic gain control attenuation ................................... 170 3ah agc1 automatic gain control 1 ................................................... 171 3bh agc2 automatic gain control 2 ................................................... 172 3ch agc3 automatic gain control 3 ................................................... 173 3dh agc4 automatic gain control 4 ................................................... 174 3eh agc5 automatic gain control 5 ................................................... 175 40h r fctl file control ......................................................................... 176 41h r fcmd file command .................................................................... 177 42h r fdata file data ............................................................................. 179 43h r fptr file pointer ......................................................................... 180 47h r spsctl sps control........................................................................ 181 48h r rtc1 real time clock 1 .............................................................. 182 49h r rtc2 real time clock 2 .............................................................. 183 4ah r dout0 data out (timeslot 0) ......................................................... 184 4bh r dout1 data out (timeslot 1) ......................................................... 185 4chr dout2 data out (timeslot 2) ......................................................... 186 4dhr dout3 data out (timeslot 3 or static mode)................................. 187 4eh din data in (timeslot 3 or static mode).................................... 188 4fh r ddir data direction (timeslot 3 or static mode) ........................ 189 60h r sctl speakerphone control ....................................................... 190 62h r ssrc1 speakerphone source 1..................................................... 191 63h r ssrc2 speakerphone source 2..................................................... 192 64h ssdx1 speech detector (transmit) 1 ............................................ 193 65h ssdx2 speech detector (transmit) 2 ............................................ 194 66h ssdx3 speech detector (transmit) 3 ............................................ 195 67h ssdx4 speech detector (transmit) 4 ............................................ 196 68h ssdr1 speech detector (receive) 1 ............................................. 197
psb 4860 detailed register description semiconductor group 117 10.97 69h ssdr2 speech detector (receive) 2 ............................................. 198 6ah ssdr3 speech detector (receive) 3 ............................................. 199 6bh ssdr4 speech detector (receive) 4 ............................................. 200 6ch sscas1 speech comparator (acoustic side) 1 ............................... 201 6dh sscas2 speech comparator (acoustic side) 2 ............................... 202 6eh sscas3 speech comparator (acoustic side) 3 ............................... 203 6fh sscls1 speech comparator (line side) 1...................................... 204 70h sscls2 speech comparator (line side) 2...................................... 205 71h sscls3 speech comparator (line side) 3...................................... 206 72h satt1 attenuation unit 1............................................................... 207 73h satt2 attenuation unit 2............................................................... 208 74h sagx1 automatic gain control (transmit) 1.................................. 209 75h sagx2 automatic gain control (transmit) 2.................................. 210 76h sagx3 automatic gain control (transmit) 3.................................. 211 77h sagx4 automatic gain control (transmit) 4.................................. 212 78h sagx5 automatic gain control (transmit) 5.................................. 213 79h sagr1 automatic gain control (receive) 1................................... 214 7ah sagr2 automatic gain control (receive) 2................................... 215 7bh sagr3 automatic gain control (receive) 3................................... 216 7ch sagr4 automatic gain control (receive) 4................................... 217 7dh sagr5 automatic gain control (receive) 5................................... 218 7eh slga line gain ............................................................................ 219 80h saelen acoustic echo cancellation length.................................... 220 81h saeatt acoustic echo cancellation double talk attenuation ........ 221 82h saegs acoustic echo cancellation global scale .......................... 222 83h saeps1 acoustic echo cancellation partial scale........................... 223 84h saeps2 acoustic echo cancellation first block .............................. 224 note: registers cctl, fctl, fcmd, fdata, fptr, rtc1, rtc2, dout0, dout1, dout2, dout3 and ddir are only affected by reset, not by wakeup. for register spsctl see the register description for the exact behaviour. 3.3.2 register naming conventions several registers contain one or more fields for input signal selection. all fields labelled i 1 (i 2 , i 3 ) are five bits wide and use the same coding as shown in table 86. table 86 signal encoding 4 3 2 1 0 signal description 00000s 0 silence 00001s 1 analog line input (channel 1 of psb 4851 interface)
psb 4860 detailed register description semiconductor group 118 10.97 00010s 2 analog line output (channel 1 of psb 4851 interface) 00011s 3 microphone input (channel 2 of psb 4851 interface) 00100s 4 loudspeaker/handset output (channel 2 of psb 4851 interface) 00101s 5 serial interface input, channel 1 00110s 6 serial interface output, channel 1 00111s 7 serial interface input, channel 2 01000s 8 serial interface output, channel 2 01001s 9 dtmf generator output 01010s 10 dtmf generator auxiliary output 01011s 11 speakerphone output (acoustic side) 01100s 12 speakerphone output (line side) 01101s 13 speech decoder output 01110s 14 universal attenuator output 01111s 15 line echo canceller output 10000s 16 agc unit output (after agc) 10001s 17 agc unit output (before agc) 10010s 18 equalizer output 10011 reserved 1 0 1 - - reserved 1 1 - - - reserved table 86 signal encoding 4 3 2 1 0 signal description
psb 4860 detailed register description semiconductor group 119 10.97 00 h rev revision the revision register can only be read. for the psb 4860, v2.1, all bits except bit 12 are zero. note: a write access to the revision register does not alter its content. it does, however, reset the abt bit of the status register. 15 0 0001000000000000
psb 4860 detailed register description semiconductor group 120 10.97 01 h r cctl chip control mv voice prompt directory 0: not available 1: available (within eprom or flash) pd power down 0: psb 4860 is in active mode 1: enter power-down mode mq memory quality 0: aram 1: dram mt memory type cs9 cas selection 0: other memory 1: 256kx4 or 512kx8 memory sas split address space 0: other aram/dram 1: two 2mx8 devices 15 0 0000mv00pd000mq mt cs9sas reset value 0000000000000000 3 2 description 0 0 aram/dram 1 1 samsung flash memory
psb 4860 detailed register description semiconductor group 121 10.97 02 h r intm interrupt mask register if a bit of this register is reset (set to 0), the corresponding bit of the status register does not generate an interrupt. if a bit is set (set to 1), an external interrupt can be generated by the corresponding bit of the status register. 15 0 rdy 1 0 0 cia cd cpt cng sd err bsy dtv atv 0 0 0 reset value 0100000000000000
psb 4860 detailed register description semiconductor group 122 10.97 03 h r afectl analog front end interface control als loudspeaker amplification this value is transferred on channel c3 of the afe interface. if the psb 4851 is used it represents the amplification of the loudspeaker amplifier. en interface enable 0: afe interface disabled 1: afe interface enabled 15 0 0000 als 0000000en reset value 0000 0 00000000
psb 4860 detailed register description semiconductor group 123 10.97 04 h r ifs1 interface select 1 the signal selection fields i1, i2 and i3 of ifs1 determine the outgoing signal of channel 1 of the analog interface. for the psb 4851 this is usually the line out signal. the hp bit enables a high-pass for the incoming signal of channel 1 of the analog interface. for the psb 4851 this is usually the line in signal. hp high-pass for s 1 0: disabled 1: enabled i1 input signal 1 for ig2 i2 input signal 2 for ig2 i3 input signal 3 for ig2 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 00 0 0
psb 4860 detailed register description semiconductor group 124 10.97 05 h r ifg1 interface gain 1 ifg1 is associated with the incoming signal of channel 1 of the analog interface. for the psb 4851 this is usually the line in signal. ig1 in order to obtain a gain g the parameter ig1 can be calculated by the following formula: 15 0 0ig1 reset value 0 8192 (0 db) ig1 32768 g 12.04 db C () 20 db 10 =
psb 4860 detailed register description semiconductor group 125 10.97 06 h r ifg2 interface gain 2 ifg2 is associated with the outgoing signal of channel 1 of the analog interface. for the psb 4851 this is usually the line out signal. ig2 gain of amplifier ig2 in order to obtain a gain g the parameter ig2 can be calculated by the following formula: 15 0 0ig2 reset value 0 8192 (0 db) ig2 32768 g 12.04 db C () 20 db 10 =
psb 4860 detailed register description semiconductor group 126 10.97 07 h r ifs2 interface select 2 the signal selection fields i1, i2 and i3 of ifs2 determine the outgoing signal of channel 2 of the analog interface. for the psb 4851 this is usually the loudspeaker signal. the hp bit enables a high-pass for the incoming signal of channel 2 of the analog interface. for the psb 4851 this is usually the microphone signal. hp high-pass for s 3 0: disabled 1: enabled i1 input signal 1 for ig4 i2 input signal 2 for ig4 i3 input signal 3 for ig4 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 00 0 0
psb 4860 detailed register description semiconductor group 127 10.97 08 h r ifg3 interface gain 3 ifg3 is associated with the incoming signal of channel 2 of the analog interface. for the psb 4851 this is usually the microphone signal. ig3 gain of amplifier ig3 in order to obtain a gain g the parameter ig3 can be calculated by the following formula: 15 0 0ig3 reset value 0 8192 (0 db) ig3 32768 g 12.04 db C () 20 db 10 =
psb 4860 detailed register description semiconductor group 128 10.97 09 h r ifg4 interface gain 4 ifg4 is associated with the outgoing signal of channel 2 of the analog interface. for the psb 4851 this is usually the loudspeaker signal. ig4 gain of amplifier ig4 in order to obtain a gain g the parameter ig4 can be calculated by the following formula: 15 0 0ig4 reset value 0 8192 (0 db) ig4 32768 g 12.04 db C () 20 db 10 =
psb 4860 detailed register description semiconductor group 129 10.97 0a h r sdconf serial data interface configuration nts number of timeslots dcl double clock mode 0: single clock mode 1: double clock mode en enable interface 0: interface is disabled (both channels) 1: interface is enabled (depending on separate channel enable bits) 15 0 00 nts 00000dcl0en reset value 00 0 00000000 13 12 11 10 9 8 description 0000001 0000012 ... ... ... ... ... ... ... 11111164
psb 4860 detailed register description semiconductor group 130 10.97 0b h r sdchn1 serial data interface channel 1 nas number of active drst strobe (ssdi interface mode) pcd pcm code 0: a-law 1: m -law en enable interface 0: interface is disabled 1: interface is enabled if sdconf:en=1 pcm pcm mode 0: 16 bit linear coding (two timeslots) 1: 8 bit pcm coding (one timeslot) dd data direction 0: dd: data downstream, du: data upstream 1: dd: data upstream, du: data downstream ts timeslot for channel 1 15 0 nas 0 0 pcd en pcm dd ts reset value 0 000000 0 15 14 13 12 description 00001 ... ... ... ... ... 111116 543210description 0000000 ... ... ... ... ... ... ... 11111163
psb 4860 detailed register description semiconductor group 131 10.97 note: if pcm=0 then ts denotes the first timeslot of the two consecutive timeslots used. only even timeslots are allowed in this case.
psb 4860 detailed register description semiconductor group 132 10.97 0c h r ifs3 interface select 3 the signal selection fields i1, i2 and i3 of ifs3 determine the outgoing signal of channel 1 of the iom/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 1 of the analog iom/ ssdi-interface. hp high-pass for s 6 0: disabled 1: enabled i1 input signal 1 for s 5 i2 input signal 2 for s 5 i3 input signal 3 for s 5 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 00 0 0
psb 4860 detailed register description semiconductor group 133 10.97 0d h r sdchn2 serial data interface channel 2 pcd pcm code 0: a-law 1: m -law en enable interface 0: interface is disabled 1: interface is enabled if sdconf:en=1 pcm pcm mode 0: 16 bit linear coding (two timeslots) 1: 8 bit pcm coding (one timeslot) dd data direction 0: dd: data downstream, du: data upstream 1: dd: data upstream, dd: data downstream ts timeslot for channel 2 note: if pcm=0 then ts denotes the first timeslot of the two consecutive timeslots used. only even timeslots are allowed in this case. 15 0 000000pcdenpcmdd ts reset value 0000000000 0 5 4 3 2 1 0 description 0000000 0000011 ... ... ... ... ... ... ... 11111163
psb 4860 detailed register description semiconductor group 134 10.97 0e h r ifs4 interface select 4 the signal selection fields i1, i2 and i3 of ifs4 determine the outgoing signal of channel 2 of the iom/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 2. hp high-pass for s 7 0: disabled 1: enabled i1 input signal 1 for s 8 i2 input signal 2 for s 8 i3 input signal 3 for s 8 as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 00 0 0
psb 4860 detailed register description semiconductor group 135 10.97 0f h r ifg5 interface gain 5 att1 attenuation for i3 (channel 1) in order to obtain an attenuation a the parameter att1 can be calculated by the following formula: att2 attenuation for i3 (channel 2) in order to obtain an attenuation a the parameter att2 can be calculated by the following formula: 15 0 att1 att2 reset value 255 (0 db) 255 (0 db) att1 256 a20db 10 = att2 256 a20db 10 =
psb 4860 detailed register description semiconductor group 136 10.97 10 h r ua universal attenuator att attenuation for ua for a given attenuation a [db] the parameter att can be calculated by the following formula: i1 input selection for ua 15 0 att 000 i1 reset value 0 (-100 db) 0 0 0 0 att 256 a20db 10 =
psb 4860 detailed register description semiconductor group 137 10.97 11 h r dgctl dtmf generator control en generator enable 0: disabled 1: enabled md mode 0: raw 1: cooked dtc dial tone code (cooked mode) 15 0 enmd0000000000 dtc reset value 000000000000 0 3 2 1 0 digit frequency 0 0 0 0 1 697/1209 0 0 0 1 2 697/1336 0 0 1 0 3 697/1477 0 0 1 1 a 697/1633 0 1 0 0 4 770/1209 0 1 0 1 5 770/1336 0 1 1 0 6 770/1477 0 1 1 1 b 770/1633 1 0 0 0 7 852/1209 1 0 0 1 8 852/1336 1 0 1 0 9 852/1477 1 0 1 1 c 852/1633 1 1 0 0 * 941/1209 1 1 0 1 0 941/1336 1 1 1 0 # 941/1477 1 1 1 1 d 941/1633
psb 4860 detailed register description semiconductor group 138 10.97 12 h dgf1 dtmf generator frequency 1 frq frequency of generator 1 the parameter frq for a given frequency f [hz] can be calculated by the following formula: 15 0 0 frq frq 32768 f 4000hz ------------------- =
psb 4860 detailed register description semiconductor group 139 10.97 13 h dgf2 dtmf generator frequency 2 frq frequency of generator 2 he parameter frq for a given frequency f [hz] can be calculated by the following formula: 15 0 0frq frq 32768 f 4000hz ------------------- =
psb 4860 detailed register description semiconductor group 140 10.97 14 h dgl dtmf generator level lev2 signal level of generator 2 in order to obtain a signal level l (relative to the pcm maximum value) for generator 2 the value of lev2 can be calculated according to the following formula: lev1 signal level of generator 1 in order to obtain a signal level l (relative to the pcm maximum value) for generator 1 the value of lev1 can be calculated according to the following formula: 15 0 0 lev2 0 lev1 lev2 128 l20db 10 = lev1 128 l20db 10 =
psb 4860 detailed register description semiconductor group 141 10.97 15 h dgatt dtmf generator attenuation att2 attenuation of signal s 10 in order to obtain attenuation a the parameter att2 can be calculated by the formula: att1 attenuation of signal s 9 in order to obtain attenuation a the parameter att1 can be calculated by the formula: 15 0 att2 att1 att2 128 1024 a20db 10 +a181db , > ; 128 a20db 10 a 18 1 db , < ; ? = att1 128 1024 a20db 10 +a181db , > ; 128 a20db 10 a 18 1 db , < ; ? =
psb 4860 detailed register description semiconductor group 142 10.97 16 h r cngctl calling tone control en enable 0: cng unit disabled 1: cng unit enabled i1 input selection for calling tone detector 15 0 en0000000000 i1 reset value 00000000000 0
psb 4860 detailed register description semiconductor group 143 10.97 17 h cngbt cng burst time time minimum time for calling tone in order to obtain the parameter time for a minimum time t the following formula can be used: 15 0 0 time time t 0.125 ms =
psb 4860 detailed register description semiconductor group 144 10.97 18 h cnglev cng minimal signal level min minimum signal level for calling tone in order to obtain the parameter min for a minimum signal level l the following formula can be used: 15 0 00 min min 16384 l20db 10 =
psb 4860 detailed register description semiconductor group 145 10.97 19 h cngres cng signal resolution res signal resolution the parameter res depends on the noise level l as follows: 15 0 1111 res res 4096 C l20db 10 =
psb 4860 detailed register description semiconductor group 146 10.97 1a h r atdctl0 alert tone detection 0 en enable alert tone detection 0: the alert tone detection is disabled 1: the alert tone detection is enabled i1 input signal selection atc alert tone code 1) undefined 15 0 en00 i1 000000 atc reset value 000 0 000000 - 1) 1 0 description 0 0 no tone 0 1 2130 1 0 2750 1 1 2130/2750
psb 4860 detailed register description semiconductor group 147 10.97 1b h atdctl1 alert tone detection 1 md alert tone detection mode 0: only dual tones will be detected 1: either dual or single tones will be detected dev maximum frequency deviation for alert tone 0: 0.5% 1: 1.1% min minimum level of alert tone signal for a minimum signal level min the parameter min is given by the following formula: 15 0 md00dev0000 min min 2560 min 20 db 10 =
psb 4860 detailed register description semiconductor group 148 10.97 1c h r cidctl0 caller id control 0 en cid enable 0: disabled 1: enabled i1 input signal selection data last received data byte 15 0 en 0 0 i1 data reset value 000 0 0
psb 4860 detailed register description semiconductor group 149 10.97 1d h cidctl1 caller id control 1 nmb minimum number of mark bits nmss minimum number of mark/space sequences min minimum signal level for cid decoder for a minimum signal level min the parameter min is given by the following formula: 15 0 nmb nmss min 15 14 13 12 11 10 description 0000000 000 110 ... ... ... ... ... ... ... 111111630 9 8 7 6 5 description 000001 0000111 ... ... ... ... ... 11111311 min 640 min 20 db 10 =
psb 4860 detailed register description semiconductor group 150 10.97 20 h r cptctl call progress tone control en cpt detector enable 0: disabled 1: enabled md cpt mode 0: raw 1: cooked i1 input signal selection 15 0 enmd000000000 i1 reset value 00000000000 0
psb 4860 detailed register description semiconductor group 151 10.97 21 h cpttr call progress tone thresholds num number of cycles sn minimal signal-to-noise ratio min minimum signal level for cpt detector 15 0 num 0 sn min 15 14 13 cooked mode raw mode 0 0 0 reserved 0 0 0 1 2 reserved ... ... ... ... reserved 1 1 1 8 reserved 11 10 9 8 description 11119db 100012db 010015db 001018db 000022db value description 89 h -40 db 85 h -42 db 80 h -44 db 9a h -46 db 95 h -48 db 90 h -50 db
psb 4860 detailed register description semiconductor group 152 10.97 22 h cptmn cpt minimum times minb minimum time for cpt burst the parameter minb for a minimal burst time tbmin can be calculated by the following formula: ming minimum time for cpt gap the parameter ming for a minimal burst time tgmin can be calculated by the following formula: 15 0 minb ming minb tbmin 32 ms C 4 ------------------------------------- - = ming tgmin 32 ms C 4 -------------------------------------- =
psb 4860 detailed register description semiconductor group 153 10.97 23 h cptmx cpt maximum times maxb maximum time for cpt burst the parameter maxb for a maximal burst time of tbmax can be calculated by the following formula: maxg maximum time for cpt gap the parameter maxg for a maximal burst time of tgmax can be calculated by the following formula: 15 0 maxb maxg maxb tbmax tbmin C 8 ----------------------------------------- = maxg tgmax tgmin C 8 ----------------------------------------- - =
psb 4860 detailed register description semiconductor group 154 10.97 24 h cptdt cpt delta times difb maximum time difference between consecutive bursts the parameter difb for a maximal difference of t ms of two burst durations can be calculated by the following formula: difg maximum time difference between consecutive gaps the parameter difg for a maximal difference of t ms of two gap durations can be calculated by the following formula: 15 0 difb difg difb t 2ms ----------- = difg t 2ms ----------- =
psb 4860 detailed register description semiconductor group 155 10.97 25 h r lecctl line echo cancellation control en enable 0: disabled 1: enabled md mode 0: normal 1: extended i1 input signal selection for i 1 i2 input signal selection for i 2 15 0 enmd0000 i1 i2 reset value 000000 0 0
psb 4860 detailed register description semiconductor group 156 10.97 26 h leclev minimal signal level for line echo cancellation min the parameter min for a minimal signal level l (db) can be calculated by the following formula: 15 0 0min min 512 96.3 l + () 5log2 ---------------------------------------- =
psb 4860 detailed register description semiconductor group 157 10.97 27 h lecatt externally provided attenuation att the parameter att for an externally provided attenuation a (db) can be calculated by the following formula: 15 0 0att att 512 a 5log2 ------------------- =
psb 4860 detailed register description semiconductor group 158 10.97 28 h lecmgn margin for double talk detection mgn the parameter mgn for a margin of l (db) can be calculated by the following formula: 15 0 0mgn mgn 512 l 5log2 ------------------- =
psb 4860 detailed register description semiconductor group 159 10.97 29 h r ddctl dtmf detector control en enable dtmf tone detection 0: the dtmf detection is disabled 1: the dtmf detection is enabled i1 input signal selection dtc dtmf tone code 1) undefined 15 0 en00 i1 000 dtc reset value 0000000- 1) 4 3 2 1 0 frequency digit 1 0 0 0 0 941 / 1633 d 1 0 0 0 1 697 / 1209 1 1 0 0 1 0 697 / 1336 2 1 0 0 1 1 697 / 1477 3 1 0 1 0 0 770 / 1209 4 1 0 1 0 1 770 / 1336 5 1 0 1 1 0 770 / 1477 6 1 0 1 1 1 852 / 1209 7 1 1 0 0 0 852 / 1336 8 1 1 0 0 1 852 / 1477 9 1 1 0 1 0 941 / 1336 0 1 1 0 1 1 941 / 1209 * 1 1 1 0 0 941 / 1477 # 1 1 1 0 1 697 / 1633 a 1 1 1 1 0 770 / 1633 b 1 1 1 1 1 852 / 1633 c
psb 4860 detailed register description semiconductor group 160 10.97 2a h ddtw dtmf detector signal twist twist signal twist for dtmf tone in order to obtain a minimal signal twist t the parameter twist can be calculated by the following formula: note: twist must be in the range [4096,20480] 15 0 0twist twist 32768 0.5 db t C () 10 db 10 =
psb 4860 detailed register description semiconductor group 161 10.97 2b h ddlev dtmf detector minimum signal level min minimum signal level note: values outside the given range are reserved and must not be used. 15 0 1111111111 min 5 4 3 2 1 0 description 001110 -50db 001111 -49db ... ... ... ... ... ... ... 100001 -31db 100010 -30db
psb 4860 detailed register description semiconductor group 162 10.97 2e h r fcfctl equalizer control en enable equalizer 0: the equalizer is disabled 1: the equalizer is enabled adr coefficient address 15 0 en0 adr 000 i reset value 00 0 000 0 13 12 11 10 9 8 coefficient 000000 a1 000001 a2 000010 a3 000011 a4 000100 a5 000101 a6 000110 a7 000111 a8 001000 a9 001001 b2 001010 b3 001011 b4 001100 b5 001101 b6 001 110 b7 001111 b8 010000 b9 010001 c1 010010 d1 010011 d2 010100 d3 010101 d4 01 0110 d5
psb 4860 detailed register description semiconductor group 163 10.97 i1 input signal selection 010111 d6 011000 d7 011001 d8 011010 d9 011011 d10 011100 d11 011101 d12 01 1 110 d13 011111 d14 100000 d15 100001 d16 100010 d17 100011 c2 13 12 11 10 9 8 coefficient
psb 4860 detailed register description semiconductor group 164 10.97 2f h fcfcof equalizer coefficient data v coefficient value for the coefficient a 1 -a 9 , b 2 -b 9 and d 1 -d 17 the following formula can be used to calculate v for a coefficient c : for the coefficients c 1 and c 2 the following formula can be used to calculate v for a coefficient c : 15 0 v v 32768 c =; -1c1 < v128c = ; 1 c 256 <
psb 4860 detailed register description semiconductor group 165 10.97 30 h r scctl speech coder control en enable 0: disabled 1: enabled hq high quality mode 0: long play mode 1: high quality mode vc voice controlled start of recording 0: disabled 1: enabled i1 input signal selection (first input) i2 input signal selection (second input) 15 0 en hq vc 0 0 0 i1 i2 reset value 000000 0 0
psb 4860 detailed register description semiconductor group 166 10.97 31 h scct2 speech coder control 2 time the parameter time for a time t ([ms]) can be calculated by the following formula: min the parameter min for a signal level l ([db]) can be calculated by the following formula: 15 0 time min time t 32 ----- - = min 16384 l 20 ----- - 10 =
psb 4860 detailed register description semiconductor group 167 10.97 32 h scct3 speech coder control 3 lp the parameter lp for a time constant of t ([ms]) can be calculated by the following formula: 15 0 0 lp 00000000 lp 256 t -------- - =
psb 4860 detailed register description semiconductor group 168 10.97 34 h r sdctl speech decoder control en enable 0: disabled 1: enabled speed playback speed 15 0 en000000000000 speed reset value 00000000000000 0 1 0 description 0 0 normal speed 0 1 0.5 times normal speed 1 0 1.5 times normal speed 1 1 2.0 times normal speed
psb 4860 detailed register description semiconductor group 169 10.97 38 h r agcctl agc control en enable 0: disabled 1: enabled i1 input signal selection for i 1 i2 input signal selection for i 2 15 0 en00000 i1 i2 reset value 000000 0 0
psb 4860 detailed register description semiconductor group 170 10.97 39 h r agcatt automatic gain control attenuation att the parameter att for an attenuation a ([db]) can be calculated by the following formula: 15 0 att reset value 0 (-100 db) att 32768 a 20 ----- - 10 =
psb 4860 detailed register description semiconductor group 171 10.97 3a h agc1 automatic gain control 1 com the parameter com for a signal level l ([db]) can be calculated by the following formula: ag_init in order to obtain an initial gain g ([db]) the parameter ag_init can be calculated by the following formula: 15 0 com ag_init com 128 10 + l6622 , + 20 ------------------------ - l -42,14 db < ; 10 l4214 , + 20 ------------------------ - l -42,14 db > ; ? ? ? = ag_init 128 10 + g1806 , + 20 ------------------------- g 6 02 db , < ; 10 g602 , C 20 --------------------- - g 6 02 db , > ; ? ? ? =
psb 4860 detailed register description semiconductor group 172 10.97 3b h agc2 automatic gain control 2 speedl the parameter speedl for a multiplication factor m is given by the following formula: speedh the parameter speedh for a multiplication factor m is given by the following formula: 15 0 speedl speedh speedl m 8192 ----------- - = speedh m 256 -------- - =
psb 4860 detailed register description semiconductor group 173 10.97 3c h agc3 automatic gain control 3 min the parameter min for a gain g ([db]) can be calculated by the following formula: max the parameter max for an attenuation a ([db]) can be calculated by the following formula: 15 0 min max min 128 10 + g1806 , + 20 ------------------------- g 6 02 db , < ; 10 g602 , C 20 --------------------- - g 6 02 db , > ; ? ? ? = max 10 a4214 , + 20 ------------------------- =
psb 4860 detailed register description semiconductor group 174 10.97 3d h agc4 automatic gain control 4 dec the parameter dec for a time constant t ([1/ms]) is given by the following formula: lim the parameter lim for a signal level l ([db]) can be calculated by the following formula: 15 0 dec lim dec 256 t -------- - = lim 128 10 + l903 , + 20 --------------------- - l 66,22 db < ; 10 l6622 , + 20 ------------------------ - l 66,22 db > ; ? ? ? =
psb 4860 detailed register description semiconductor group 175 10.97 3e h agc5 automatic gain control 5 lp the parameter lp for a time constant t ([1/ms]) is given by the following formula: 15 0 000000001 lp lp 16 t ----- - =
psb 4860 detailed register description semiconductor group 176 10.97 40 h r fctl file control md mode 0: audio mode 1: binary mode ms memory space 0: r/w memory 1: voice prompt directory ts time stamp 0: no update of rtc1/rtc2 entry of file descriptor 1: rtc1/rtc2 entries are updated by content of rtc1/rtc2 registers. fno file number 15 0 0mdmsts0000 fno reset value 00000000 0
psb 4860 detailed register description semiconductor group 177 10.97 41 h r fcmd file command in initialize 0: no 1: yes (if cmd=1111) rd remap directory 0: no 1: yes abt abort command 0: no 1: abort recompress eie enable immediate execution 0: disabled (default, always possible) 1: enabled (restricted to certain commands and operating modes) cmd file command 15 0 0inrd00000abteie0 cmd reset value 00000000000 0 4 3 2 1 0 description 0 0 0 0 0 open file 00001activate 0 0 0 1 0 seek 00011cut file 0 0 1 0 0 read data 00101write data 0 0 1 1 0 memory status 0 0 1 1 1 recompress file 0 1 0 0 0 read file descriptor - user 0 1 0 0 1 write file descriptor - user
psb 4860 detailed register description semiconductor group 178 10.97 0 1 0 1 0 read file descriptor - rtc1 0 1 0 1 1 read file descriptor - rtc2 0 1 1 0 0 read file descriptor - len 0 1 1 0 1 garbage collection 0 1 1 1 0 open next free file 0 1 1 1 1 initialize 10000dma read 1 0 0 0 1 dma write 1 0 0 1 0 erase block 1 0 0 1 1 set address 1 0 1 - - reserved 1 1 0 - - reserved 1 1 1 - - reserved 4 3 2 1 0 description
psb 4860 detailed register description semiconductor group 179 10.97 42 h r fdata file data the fdata register contains the following information after a memory status command: free free blocks number of blocks (1 kbyte) currently usable for recording. 15 0 free reset value 0
psb 4860 detailed register description semiconductor group 180 10.97 43 h r fptr file pointer 15 0 file pointer 0 0 0 0 0 phrase selector reset value 0
psb 4860 detailed register description semiconductor group 181 10.97 47h r spsctl sps control pos position of status register window mode mode of sps interface sp1 direct control for sps 1 0: sps 1 set to 0 1: sps 1 set to 1 sp0 direct control for sps 0 0: sps 0 set to 0 1: sps 0 set to 1 note: if mode 1 has been selected prior to power-down, both mode 1 and the values of sp1 and sp0 are retained during power-down and wake-up. other modes are reset to 0 during power down. 1) undefined 15 0 pos 0 0 0 0 0 0 0 mode sp1 sp0 reset value 0 0000000 0 - 1) - 1) 15 14 13 12 sps 0 sps 1 0 0 0 0 bit 0 bit 1 0 0 0 1 bit 1 bit 2 ... ... ... ... ... ... 1 1 1 0 bit 14 bit 15 4 3 2 description 0 0 0 disabled (sps 0 and sps 1 zero) 0 0 1 output of sp1 and sp0 1 0 0 output of speakerphone state 1 0 1 expanded address output 1 1 0 output of status register
psb 4860 detailed register description semiconductor group 182 10.97 48 h r rtc1 real time clock 1 min minutes number of minutes elapsed in the current hour (0-59). sec seconds number of seconds elapsed in the current minute (0-59). 15 0 0000 min sec reset value 0000 0 0
psb 4860 detailed register description semiconductor group 183 10.97 49 h r rtc2 real time clock 2 day days number of days elapsed since last reset (0-2047). hr hours number of hours elapsed in the current day (0-23). 15 0 day hr reset value 00
psb 4860 detailed register description semiconductor group 184 10.97 4a h r dout0 data out (timeslot 0) data output data output data for pins ma 0 -ma 11 while ma 12 =1 (only if hwconfig1:app=10). note: this register cannot be read. 15 0 0000 data reset value 0000 0
psb 4860 detailed register description semiconductor group 185 10.97 4b h r dout1 data out (timeslot 1) data output data output data for pins ma 0 -ma 11 while ma 13 =1 (only if hwconfig1:app=10). note: this register cannot be read. 15 0 0000 data reset value 0000 0
psb 4860 detailed register description semiconductor group 186 10.97 4c h r dout2 data out (timeslot 2) data output data output data for pins ma 0 -ma 11 while ma 14 =1 (only if hwconfig1:app=10). note: this register cannot be read. 15 0 0000 data reset value 0000 0
psb 4860 detailed register description semiconductor group 187 10.97 4d h r dout3 data out (timeslot 3 or static mode) data output data output data for pins ma 0 -ma 11 while ma 15 =1 (only if hwconfig1:app=10). output data for pins ma 0 -ma 15 (only if hwconfig1:app=01) note: this register cannot be read. 15 0 data reset value 0
psb 4860 detailed register description semiconductor group 188 10.97 4e h din data in (timeslot 3 or static mode) data input data input data for pins ma 0 -ma 11 at falling edge of ma 12 (only if hwconfig1:app=10). input data for pins ma 0 -ma 15 (only if hwconfig1:app=01) 15 0 data
psb 4860 detailed register description semiconductor group 189 10.97 4f h r ddir data direction (timeslot 3 or static mode) dir port direction port direction during ma 12 =1 or in static mode. 0: input 1: output note: this register cannot be read. 15 0 dir reset value 0 (all inputs)
psb 4860 detailed register description semiconductor group 190 10.97 60 h r sctl speakerphone control ens enable echo suppression 0: the echo suppression unit is disabled 1: the echo suppression unit is enabled enc enable echo cancellation 0: the echo cancellation unit is disabled 1: the echo cancellation unit is enabled md mode 0: speakerphone mode 1: loudhearing mode sdr signal source of sdr 0: after agcr 1: before agcr sdx signal source of sdx 0: after agcx 1: before agcx agr agcr enable 0: agcr disabled 1: agcr enabled agx agcx enable 0: agcx disabled 1: agcx enabled 15 0 ensenc000000mdsdrsdx00agragx0 reset value 0000000000000000
psb 4860 detailed register description semiconductor group 191 10.97 62 h r ssrc1 speakerphone source 1 i1 input signal selection (acoustic source 1) i2 input signal selection (acoustic source 2) 15 0 000000 i1 i2 reset value 000000 0 0
psb 4860 detailed register description semiconductor group 192 10.97 63 h r ssrc2 speakerphone source 2 i3 input signal selection (line source 1) i4 input signal selection (line source 2) 15 0 000000 i3 i4 reset value 000000 0 0
psb 4860 detailed register description semiconductor group 193 10.97 64 h ssdx1 speech detector (transmit) 1 lp2l the parameter lp2l for a saturation level l (db) can be calculated by the following formula: lim the parameter lim for a minimum signal level l (db, relative to pcm max. value) can be calculated by the following formula: 15 0 0 lp2l 0 lim lp2l 2l 5log2 ------------------- = lim 296.3l + () 5log2 ---------------------------------- =
psb 4860 detailed register description semiconductor group 194 10.97 65 h ssdx2 speech detector (transmit) 2 lp1 the parameter lp1 for a time t (ms) can be calculated by the following formula: off the parameter off for a level offset of o (db) can be calculated by the following formula: 15 0 lp1 0 off lp1 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? = off 2o 5 log2 ------------------- =
psb 4860 detailed register description semiconductor group 195 10.97 66 h ssdx3 speech detector (transmit) 3 pdn the parameter pdn for a time t (ms) can be calculated by the following formula: lp2n the parameter lp2n for a time t (ms) can be calculated by the following formula: 15 0 pdn lp2n pdn 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? = lp2n 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? =
psb 4860 detailed register description semiconductor group 196 10.97 67 h ssdx4 speech detector (transmit) 4 pds the parameter pds for a time t (ms) can be calculated by the following formula: lp2s the parameter lp2s for a time t (ms) can be calculated by the following formula: 15 0 pds 0 lp2s pds 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? = lp2s 262144 t ----------------- - =
psb 4860 detailed register description semiconductor group 197 10.97 68 h ssdr1 speech detector (receive) 1 lp2l the parameter lp2l for a saturation level l (db) can be calculated by the following formula: lim the parameter lim for a minimum signal level l (db, relative to pcm max. value) can be calculated by the following formula: 15 0 0 lp2l 0 lim lp2l 2l 5log2 ------------------- = lim 296.3l + () 5log2 ---------------------------------- =
psb 4860 detailed register description semiconductor group 198 10.97 69 h ssdr2 speech detector (receive) 2 lp1 the parameter lp1 for a time t (ms) can be calculated by the following formula: off the parameter off for a level offset of o (db) can be calculated by the following formula: 15 0 lp1 0 off lp1 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? = off 2o 5 log2 ------------------- =
psb 4860 detailed register description semiconductor group 199 10.97 6a h ssdr3 speech detector (receive) 3 pdn the parameter pdn for a time t (ms) can be calculated by the following formula: lp2n the parameter lp2n for a time t (ms) can be calculated by the following formula: 15 0 pdn lp2n pdn 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? = lp2n 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? =
psb 4860 detailed register description semiconductor group 200 10.97 6b h ssdr4 speech detector (receive) 4 pds the parameter pds for a time t (ms) can be calculated by the following formula: lp2s the parameter lp2s for a time t (ms) can be calculated by the following formula: 15 0 pds 0 lp2s pds 64 t 0.5 t 64 << ; 128 2048 t + 16.2 t 2048 << ; ? = lp2s 262144 t ----------------- - =
psb 4860 detailed register description semiconductor group 201 10.97 6c h sscas1 speech comparator (acoustic side) 1 g the parameter g for a gain a (db) can be calculated by the following formula: note: the parameter g is interpreted in twos complement. et the parameter et for a time t (ms) can be calculated by the following formula: 15 0 get g 2a 5log2 ------------------- = et t 4 -- - =
psb 4860 detailed register description semiconductor group 202 10.97 6d h sscas2 speech comparator (acoustic side) 2 gdn the parameter gdn for a gain g (db) can be calculated by the following formula: pdn the parameter pdn for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0gdn pdn gdn 4g 5log2 ------------------- = pdn 64 r 5log2 ------------------- =
psb 4860 detailed register description semiconductor group 203 10.97 6e h sscas3 speech comparator (acoustic side) 3 gds the parameter gds for a gain g (db) can be calculated by the following formula: pds the parameter pds for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0 gds pds gds 4g 5log2 ------------------- = pds 64 r 5log2 ------------------- =
psb 4860 detailed register description semiconductor group 204 10.97 6f h sscls1 speech comparator (line side) 1 g the parameter g for a gain a (db) can be calculated by the following formula: note: the parameter g is interpreted in twos complement. et the parameter et for a time t (ms) can be calculated by the following formula: 15 0 get g 2a 5log2 ------------------- = et t 4 -- - =
psb 4860 detailed register description semiconductor group 205 10.97 70 h sscls2 speech comparator (line side) 2 gdn the parameter gdn for a gain g (db) can be calculated by the following formula: pdn the parameter pdn for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0 gdn pdn gdn 4g 5log2 ------------------- = pdn 64 r 5log2 ------------------- =
psb 4860 detailed register description semiconductor group 206 10.97 71 h sscls3 speech comparator (line side) 3 gds the parameter gds for a gain g (db) can be calculated by the following formula: pds the parameter pds for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0gds pds gds 4g 5log2 ------------------- = pds 64 r 5 log2 ------------------- =
psb 4860 detailed register description semiconductor group 207 10.97 72 h satt1 attenuation unit 1 att the parameter att for an attenuation a (db) can be calculated by the following formula: sw the parameter sw for a switching rate r (ms/db) can be calculated by the following formula: 15 0 0att sw att 2a 5log2 ------------------- = sw 128 1 5log2 sw ----------------------------------- + 0.0053 sw 0.66 << ; 16 5log2 sw ----------------------------------- 0.66 sw 0.63 << ; ? ? ? =
psb 4860 detailed register description semiconductor group 208 10.97 73 h satt2 attenuation unit 2 tw the parameter tw for a time t (ms) can be calculated by the following formula: ds the parameter ds for a decay rate r (ms/db) can be calculated by the following formula: 15 0 tw ds tw t 16 ----- - = ds 5log2 r1 C 4 -------------------------------------- - =
psb 4860 detailed register description semiconductor group 209 10.97 74 h sagx1 automatic gain control (transmit) 1 ag_init the parameter ag_init for a gain g (db) can be calculated by the following formula: this parameter is interpreted in twos complement. com the threshold com for a level l (db) can be calculated by the following formula: 15 0 ag_init 0 com ag_init 2 Cg 5 log2 ------------------- = com 296.3l + () 5log2 ---------------------------------- =
psb 4860 detailed register description semiconductor group 210 10.97 75 h sagx2 automatic gain control (transmit) 2 ag_att the parameter ag_att for a gain g (db) can be calculated by the following formula: speedh the parameter speedh for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 0 ag_att speedh ag_att 2 Cg 5log2 ------------------- = speedh 4096 dr -------------- =
psb 4860 detailed register description semiconductor group 211 10.97 76 h sagx3 automatic gain control (transmit) 3 ag_gain the parameter ag_gain for a gain g (db) can be calculated by the following formula: speedl the parameter com for a gain g (db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 ag_gain speedl ag_gain 2 Cg 5log2 ------------------- = com 296.3g + () 5log2 ---------------------------------- - =
psb 4860 detailed register description semiconductor group 212 10.97 77 h sagx4 automatic gain control (transmit) 4 nois the parameter nois for a threshold level l (db) can be calculated by the following formula: lpa the parameter lpa for a low pass time constant t (ms) can be calculated by the following formula: 15 0 0 nois 0 lpa com 296.3l + () 5log2 ---------------------------------- = lpa 16 t ----- - =
psb 4860 detailed register description semiconductor group 213 10.97 78 h sagx5 automatic gain control (transmit) 5 ag_cur the current gain g of the agc can be derived from the parameter parameter ag_cur by the following formula: ag_cur is interpreted in twos complement. 15 0 ag_cur 00000000 g 5 C log2 ag_cur 2 ----------------------------------------------------- =
psb 4860 detailed register description semiconductor group 214 10.97 79 h sagr1 automatic gain control (receive) 1 ag_init the parameter ag_init for a gain g (db) can be calculated by the following formula: this parameter is interpreted in twos complement. com the parameter com for a threshold l (db) can be calculated by the following formula: 15 0 ag_init 0 com ag_init 2 Cg 5log2 ------------------- = com 296.3l + () 5log2 ---------------------------------- =
psb 4860 detailed register description semiconductor group 215 10.97 7a h sagr2 automatic gain control (receive) 2 ag_att the parameter ag_att for a gain g (db) can be calculated by the following formula: speedh the parameter speedh for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 0 ag_att speedh ag_att 2 Cg 5log2 ------------------- = speedh 4096 dr -------------- =
psb 4860 detailed register description semiconductor group 216 10.97 7b h sagr3 automatic gain control (receive) 3 ag_gain the parameter ag_gain for a gain g (db) can be calculated by the following formula: speedl the parameter speedl for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 ag_gain speedl ag_gain 2 Cg 5log2 ------------------- = speedl 4096 dr -------------- =
psb 4860 detailed register description semiconductor group 217 10.97 7c h sagr4 automatic gain control (receive) 4 nois the parameter nois for a threshold level l (db) can be calculated by the following formula: lpa the parameter lpa for a low pass time constant t (ms) can be calculated by the following formula: 15 0 0 nois 0 lpa com 296.3l + () 5log2 ---------------------------------- = lpa 16 t ----- - =
psb 4860 detailed register description semiconductor group 218 10.97 7d h sagr5 automatic gain control (receive) 5 ag_cur the current gain g of the agc can be derived from the parameter parameter ag_cur by the following formula: ag_cur is interpreted in twos complement. 15 0 ag_cur 00000000 g 5 C log2 ag_cur 2 ----------------------------------------------------- =
psb 4860 detailed register description semiconductor group 219 10.97 7e h slga line gain lgar the parameter lgar for a gain g (db) is given by the following formula: lgax the parameter lgax for a gain g (db) is given by the following formula: 15 0 0 lgar 0 lgax lgar 128 g12 C () 20 10 = lgax 128 g12 C () 20 10 =
psb 4860 detailed register description semiconductor group 220 10.97 80 h saelen acoustic echo cancellation length len len denotes the number of fir-taps used. 15 0 0000000 len
psb 4860 detailed register description semiconductor group 221 10.97 81 h saeatt acoustic echo cancellation double talk attenuation att the parameter att for an attenuation a (db) is given by the following formula: 15 0 0att att 512 a 5log2 ------------------- =
psb 4860 detailed register description semiconductor group 222 10.97 82 h saegs acoustic echo cancellation global scale gs all coefficients of the fir filter are scaled by a factor c. this factor is given by the following equation: 15 0 0000000000000 gs c2 gs =
psb 4860 detailed register description semiconductor group 223 10.97 83 h saeps1 acoustic echo cancellation partial scale ps the additional scaling coefficient ac is given by the following formula: 15 0 0000000000000 ps ac 2 ps =
psb 4860 detailed register description semiconductor group 224 10.97 84 h saeps2 acoustic echo cancellation first block fb the parameter fb denotes the first block that is affected by the partial scaling coefficient. if the partial coefficient is one, fb is disregarded. 15 0 0000000000000 fb
psb 4860 electrical characteristics semiconductor group 225 10.97 4 electrical characteristics electrical characteristics electrical characteristics 4.1 absolute maximum ratings esd integrity (according mil-std. 883d, method 3015.7): 2 kv exception: the pins int , sdx, du/dx, dd/dr, sps 0 , sps 1 and md 0 -md 7 are not protected against voltage stress >1 kv. note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.2 dc characteristics parameter symbol limit values unit ambient temperature under bias t a -20 to 85 c storage temperature t stg C 65 to125 c supply voltage v dd -0.5 to 4.2 v supply voltage v dda -0.5 to 4.2 v supply voltage v ddp -0.5 to 6 v voltage of pin with respect to ground: xtal 1 , xtal 2 v s 0 to v dda v voltage on any pin with respect to ground v s if v ddp < 3 v: C 0.4 to v dd + 0.5 if v ddp > 3 v: C 0.4 to v ddp + 0.5 v v dd / v dda = 3.3 v 0.3 v; v ddp = 5 v 10%; v ss / v ssa = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. input leakage current i il C 1.0 1.0 m a0v v in v dd h-input level (except ma 0 -ma 15 , xtal 1 ,osc 1 ) v ih1 2.0 v ddp + 0.3 v h-input level (osc 1 ) v ih2 0.8 v dd v dda + 0.3 v h-input level (ma 0 -ma 15 , mctl 1) ) v ih3 2.0 v dd v l-input level (except pins xtal 1 ,osc 1 ) v il1 C 0.3 0.8 v
psb 4860 electrical characteristics semiconductor group 226 10.97 1) mctl signals are (w /fwe , vprd /fcle, ras /foe , cas 0 /ale, cas 1 /fcs ) l-input level (osc 1 ) v il2 C 0.3 0.2 v dda v h-output level (except du/dx, dd/dr, ma 0 -ma 15 , sps 0 , sps 1 , md 0 -md 7 ) v oh1 v dd C 0.45 v i o = 2 ma h-output level (sps 0 , sps 1 , md 0 - md 7 , sdx, int ) v oh2 v dd C 0.6 v i o = 2 ma h-output level (ma 0 -ma 15 ) v oh3 v dd C 0.45 v i o = 5 ma h-output level (du/dx, dd/dr) v oh4 v dd C 0.6 v i o = 7 ma l-output level (except du/dx, dd/dr, ma 0 -ma 15 ) v ol1 0.45 v i o = C 2 ma l-output level (ma 0 -ma 15 ) (address mode or app output) v ol2 0.45 v i o = C 5 ma l-output current (ma 0 -ma 15 ) (after reset) i lo 50 150 240 m arst=1 h-output current (mctl 1) ) i ho 25 65 120 m arst=1 l-output level (pins du/dx, dd/ dr) v ol3 0.45 v i o = C 7 ma internal pullup current (frdy ) i li 350 750 1300 m a input capacitance c i 10 pf output capacitance c o 15 pf v dd supply current (power down, no refresh, no rtc) i dds1 10 50 m a v dd supply current (power down, refresh, rtc) i dds2 20 70 m a v dd supply current operating i ddo 55 70 ma v dd = 3.3 v v ddp supply current i ddp 110 m a v dd / v dda = 3.3 v 0.3 v; v ddp = 5 v 10%; v ss / v ssa = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max.
psb 4860 electrical characteristics semiconductor group 227 10.97 4.3 ac characteristics digital inputs are driven to 2.4 v for a logical 1 and to 0.45 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and 0.8 v for a logical 0. the ac- testing input/output waveforms are shown below. figure 69 input/output waveforms for ac-tests
psb 4860 electrical characteristics semiconductor group 228 10.97 dtmf detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -1.5 1.5 % frequency deviation reject 3.5 -3.5 % acceptance level -45 0 db rel. to max. pcm rejection level -50 db rel. to max. pcm twist deviation accept +/-2 +/-8 db programmable noise tolerance 12 db signal duration accept 40 ms signal duration reject 23 ms gap duration accept 18 ms cpt detector parameter symbol limit values unit test condition min. typ. max. frequency acceptance range 300 640 hz frequency rejection range 800 200 hz acceptance level -45 0 db rel. to max. pcm rejection level -50 db rel. to max. pcm signal duration accept 50 ms programmable signal duration reject 10 ms caller id decoder parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -2 2 % acceptance level -45 0 db rel. to max. pcm transmission rate 1188 1200 1212 baud noise tolerance -12 db
psb 4860 electrical characteristics semiconductor group 229 10.97 alert tone detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -0.5 0.5 % atdctl1:dev=0 frequency deviation accept -1.1 1.1 % atdctl1:dev=1 frequency deviation reject 3.5 -3.5 % acceptance level -40 0 db rel. to max. pcm rejection level -5 db rel. to acceptance level twist deviation accept +/-7 db noise tolerance 20 db signal duration accept 75 ms gap duration accept 40 ms cng detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -40 40 hz frequency deviation reject -50 50 hz acceptance level -45 0 db snr >10 db acceptance level -50 0 db snr >15 db rejection level -3 db db rel. to cnglev:min signal duration reject -1 % rel. to cngbt:time
psb 4860 electrical characteristics semiconductor group 230 10.97 status register update time the individual bits of the status register may change due to an event (like a recognized dtmf tone) or a command. the timing can be divided into four classes with these definitions the timing of the individual bits in the status register can be given as shown in table: 1) one fsc period 1) up to 30 ms if command is either sdctl:en=1 or scctl:en=1 timing diagrams table 87 status register update timing class timing comment min. max. i 0 0 immediately after command has been issued a 0 125 m s 1) command has been accepted d125 m s 250 m s deactivation time after command has been issued e - - associated event has happened bit rdy abt cia cd cpt cng sd err bsy dtv atv 0->1 aeeeeeeea 1) ee 1->0 i a a,d e,d e,d d e,d a e e,d e,d
psb 4860 electrical characteristics semiconductor group 231 10.97 figure 70 oscillator circuits recommended values oscillator circuits value unit min typ max load cl 1 40 pf static capacitance x 1 5pf motional capacitance x 1 17 ff resonance resistor x 1 60 w load cl 2 30 pf static capacitance x 2 1.7 pf motional capacitance x 2 3.5 ff resonance resistor x 2 18 40 k w frequency deviation 100 ppm xtal 1 xtal 2 c l1 c l1 x 1 osc 1 osc 2 c l2 c l2 x 2
psb 4860 electrical characteristics semiconductor group 232 10.97 figure 71 ssdi/iom ? -2 interface - bit synchronization timing figure 72 ssdi/iom ? -2 interface - frame synchronization timing parameter ssdi/iom ? -2 interface symbol limit values unit min max dcl period t 1 90 ns dcl high t 2 35 ns dcl low t 3 35 ns input data setup t 4 20 ns dd/dr dcl du/dx du/dx first bit last bit bit n bit n+1 t 4 t 6 t 7 t 8 t 5 t 2 t 1 t 3 fsc dcl t 9 t 10 t 9 t 10
psb 4860 electrical characteristics semiconductor group 233 10.97 input data hold t 5 20 ns output data from high impedance to active (fsc high or other than first timeslot) t 6 30 ns output data from active to high impedance t 7 30 ns output data delay from clock t 8 30 ns fsc setup t 9 40 ns fsc hold t 10 40 ns fsc jitter (deviation per frame) -200 200 ns parameter ssdi/iom ? -2 interface symbol limit values unit min max
psb 4860 electrical characteristics semiconductor group 234 10.97 figure 73 ssdi interface - strobe timing parameter ssdi interface symbol limit values unit min max dxst delay t 1 20 ns drst inactive setup t 2 20 ns drst inactive hold t 3 20 ns drst active setup t 4 20 ns drst active hold t 5 20 ns fsc setup t 6 8 dcl cycles fsc hold t 7 40 ns drst dcl t 4 t 5 t 2 t 3 fsc t 6 t 7 dxst t 1
psb 4860 electrical characteristics semiconductor group 235 10.97 figure 74 serial control interface parameter sci interface symbol limit values unit min max sclk cycle time t 1 500 ns sclk high time t 2 100 ns sclk low time t 3 100 ns cs setup time t 4 40 ns cs hold time t 5 10 ns sdr setup time t 6 40 ns sdr hold time t 7 40 ns sdx data out delay t 8 80 ns cs high to sdx tristate t 9 40 ns sclk to sdx active t 10 80 ns sclk to sdx tristate t 11 40 ns cs to int delay t 12 80 ns cs sclk sdr sdx int t 4 t 2 t 3 t 1 t 12 t 10 t 11 t 9 t 5 t 6 t 7 t 8
psb 4860 electrical characteristics semiconductor group 236 10.97 figure 75 analog front end interface parameter afe interface symbol limit values unit min max afeclk period t 1 125 165 ns afeclk high t 2 21/f xtal afeclk low t 3 21/f xtal afedu setup t 4 20 ns afedu hold t 5 20 ns afedd output delay t 6 30 ns afefs output delay t 7 30 ns afedu afeclk afedd bit n bit n+1 t 4 t 6 t 5 t 2 t 1 t 3 afefs t 7 t 7
psb 4860 electrical characteristics semiconductor group 237 10.97 figure 76 memory interface - dram read access parameter memory interface - dram read access symbol limit values unit min max row address setup time t 1 50 ns row address hold time t 2 50 ns column address setup time t 3 50 ns ras precharge time t 4 110 ns ras to cas delay t 5 110 2000 ns cas pulse width t 6 110 2000 ns data input setup time t 7 40 ns data input hold time t 8 0ns ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr. t 1 t 2 t 3 t 6 t 7 t 8 t 5 t 4
psb 4860 electrical characteristics semiconductor group 238 10.97 figure 77 memory interface - dram write access parameter memory interface - dram write access symbol limit values unit min max row address setup time t 1 50 ns row address hold time t 2 50 ns column address setup time t 3 50 ns ras precharge time t 4 110 ns ras to cas delay t 5 110 2000 ns cas pulse width t 6 110 2000 ns data output setup time t 7 100 ns data output hold time t 8 50 ns ras to w delay t 9 50 ns w to cas setup t 10 50 ns ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr. t 1 t 2 t 3 t 6 t 7 t 8 t 5 t 4 w t 9 t 10
psb 4860 electrical characteristics semiconductor group 239 10.97 figure 78 memory interface - dram refresh cycle note: the frequency of the dram refresh cycle depends on the selected mode. in active mode or normal refresh mode (during power down) the minimal frequency is 64 khz. in battery backup mode, the refresh frequency is 8 khz. parameter memory interface - dram refresh cycle symbol limit values unit min max ras precharge time t 1 100 ns ras low time t 2 200 5000 ns cas setup t 3 100 ns cas hold t 4 100 ns cas 0 ,cas 1 ras t 3 t 1 t 2 t 4
psb 4860 electrical characteristics semiconductor group 240 10.97 figure 79 memory interface - eprom read parameter memory interface - eprom read symbol limit values unit min max address setup before vprd t 1 110 ns vprd low time t 2 500 ns data setup time t 3 40 ns data hold time t 4 0ns ma 0 -ma 15 md 0 -md 7 vprd linear address t 1 t 2 t 3 t 4
psb 4860 electrical characteristics semiconductor group 241 10.97 figure 80 memory interface - samsung command write note: fcs stays low if other cycles follow for the same access. parameter memory interface - samsung command write symbol limit values unit min max address setup before fcs , fcle t 1 100 ns fcs low time, fcle high time t 2 400 ns fwr hold after fcle rising t 3 100 ns fwr low time t 4 200 ns fwr setup before fcle falling t 5 100 ns data setup time t 6 200 ns data hold time t 7 50 ns ma 0 -ma 11 md 0 -md 7 fcs (fcs 0 -fcs 3 ) a 16 -a 23 and fcs 0 -fcs 3 t 1 t 2 fwr fcle t 3 t 4 t 5 t 6 t 7
psb 4860 electrical characteristics semiconductor group 242 10.97 figure 81 memory interface - samsung address write parameter memory interface - samsung address write symbol limit values unit min max ale high time t 1 400 ns fwr hold after ale rising t 2 100 ns fwr low time t 3 200 ns fwr setup before ale falling t 4 100 ns data setup time t 5 200 ns data hold time t 6 50 ns md 0 -md 7 t 1 fwr ale t 2 t 3 t 4 t 5 t 6
psb 4860 electrical characteristics semiconductor group 243 10.97 figure 82 memory interface - samsung data write parameter memory interface - samsung data write symbol limit values unit min max fwr low time t 1 200 ns data setup time t 2 200 ns data hold time t 3 50 ns md 0 -md 7 fwr t 1 t 2 t 3
psb 4860 electrical characteristics semiconductor group 244 10.97 figure 83 memory interface - samsung data read parameter memory interface - samsung data read symbol limit values unit min max foe low time t 1 200 ns data setup time t 2 40 ns data hold time t 3 0ns md 0 -md 7 foe t 1 t 2 t 3
psb 4860 electrical characteristics semiconductor group 245 10.97 figure 84 auxiliary parallel port - multiplex mode parameter auxiliary port interface - multiplex mode symbol limit values unit min typ max active time (ma 0 -ma 15 ) t 1 2ms gap time (ma 0 -ma 15 ) t 2 125 m s data setup time t 3 50 ns data hold time t 4 0ns ma 0 -ma 11 ma 12 t 3 t 4 t 1 t 2 ma 13
psb 4860 electrical characteristics semiconductor group 246 10.97 figure 85 reset timing parameter reset timing symbol limit values unit min max v dd / v ddp / v dda rise time 5%-95% t 1 20 ms supply voltages stable to rst high t 2 0ns supply voltages stable to rst low t 3 0.1 ms rst high time t 4 1000 ns rst t 3 v dd / v ddp t 1 t 2 t 4
psb 4860 package outlines semiconductor group 247 10.97 5 package outlines plastic package, p-mqfp-80 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
semiconductor group 248 10.97 psb 4860 index a abort clearing event 82, 119 functional description 81 status bit 109 alert tone detector electrical characteristics 229 functional description 46 registers 146C147 status bit 110 analog front end interface electrical characteristics 236 functional description 55 registers 122C128 timing 92 aram see memory interface automatic gain control functional description 59 registers 169C175 auxiliary parallel port electrical characteristics 245 mode bits 112 multiplex mode 107 registers 184C189 static mode 107 c caller id decoder electrical characteristics 228 functional description 49 registers 148C149 status bits 109 cng detector electrical characteristics 229 functional description 45 registers 142C145 status bit 110 cpt detector electrical characteristics 228 functional description 47 registers 150C154 status bit 110 d digital interface functional description 56 mode bits 112 registers 129C135 dram see memory interface dtmf detector electrical characteristics 228 functional description 44 registers 159C161 status bit 110 dtmf generator functional description 51 registers 137C141 e eprom see memory interface equalizer functional description 61 registers 162C164 execution times file commands 77 f file commands access file descriptor 72 compress 71 create next new 69 delete 71
semiconductor group 249 10.97 psb 4860 index execution times 77 new file 69 open 69 read binary data 73 registers 176C180 restrictions 78 seek 70 status bits 110 tailcut 71 write binary data 74 type audio 64 binary 64 phrase 65 user data word 66 flash memory see memory interface g group listening 38 h hardware configuration functional description 82 registers 111 i interrupt functional description 80 pin configuration 111 register 121 iom?-2 interface electrical characteristics 232C233 functional description 86 see also: digital interface l line echo canceller functional description 42 registers 155C158 loudhearing 38 m memory interface aram/dram connection diagram 99 electrical characteristics 237C239 refresh 101, 113 timing 100 eprom connection diagram 102 electrical characteristics 240 timing 102 flash connection diagram 103 electrical characteristics 241C244 in-circuit programming 98, 113 multiple devices 104 timing 105 register 120 supported devices 98 memory management activation 68 directories 63 executiontimes 77 files 64 garbage collection 72 initialization 67 memory status 72 overview 63 status 65 o oscillator electrical characteristics 231 mode bits 112 p power down functional description 79
semiconductor group 250 10.97 psb 4860 index status bit 111 r real time clock configuration bits 111 functional description 79 oscillator 231 registers 182C183 recompression 71 reset electrical characteristics 246 functional description 79 register values 115 restrictions file commands 78 modules 83 revision functional description 82 register 119 s serial control interface command opcodes 97 electrical characteristics 235 functional description 94 signals encoding 117 reference table 117 speakerphone functional description automatic gain control 38 control 37 echo cancellation 28 echo suppression 30 overview 27 speech comparator 35 speech detector 32 registers 190C223 speech coder functional description 52 registers 165C167 speech decoder functional description 54 register 168 sps outputs functional description 38, 79 register 181 ssdi interface electrical characteristics 232C234 functional description 90 see also: digital interface status register definition 109 update timing 230 u universal attenuator functional description 58 register 136

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